VersaLogic VL-EBX-37 Reference Manual page 52

4. Write bit 0 of the analog input channel number to Bit 6, bits 2-1 of the analog input
channel number to bits 5-4, and a 2-bit input range code to bits 3-2 of SPIDATA3 (I/O
address CADh) – Any write operation to this register triggers an SPI transaction. The 2-
bit input-range codes are 0 (±5V), 1 (±10V), 2 (0 to +5V) or 3 (0 to +10V). For example,
if converting the 4th A/D channel (channel number 3) with a 0 to +5V range then
SPIDATA3 is set to 58h
5. Poll the SPI BUSY bit in the SPISTATUS register until the conversion is completed.
6. Write a '1' to ADCONVST0 Bit 0 of the FPGA ADC, DAC control/status register (I/O
address CAFh) to start a conversion
7. Poll the the ADCBUSY0 Bit 2 of the FPGA ADC/DAC control/status register (I/O
address CAFh) until this bit is a '0' (not busy) to indicate a conversion is completed (a
conversion takes a maximum of 5 µs).
8. Read the conversion data from SPIDATA3 (upper 8 bits of the 12-bit conversion) and
SPIDATA2 (lower 4 bits of the 12-bit conversion are in the upper 4 bits of this byte).
The data read is from the previous conversion not the one for the SPI values written in
Steps 1–5. Another conversion cycle is required to retrieve that data. Typically a number
of channels are sampled at one time so this conversion delay is not significant.
Anytime an SPI command is written to the A/D device a conversion must be issued for that
command. Another command will not be accepted until a conversion is performed.
EBX-37 Reference Manual
Interfaces and Connectors
46