VersaLogic VL-EBX-37 Reference Manual page 58

SPIDATA0 (READ/WRITE) CAAh (or C9Ah)
D7
MSbit
SPIDATA1 (READ/WRITE) CABh (or C9Bh)
D7
MSbit
SPIDATA2 (READ/WRITE) CACh (or C9Ch)
D7
MSbit
SPIDATA3 (READ/WRITE) CADh (or C9Dh)
D7
MSbit
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this
register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to
begin an SPI bus transaction. Increasing frame sizes from 8-bit uses the lowest address for the
least significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit
of SPIDATA3 is sent first, and received data will be shifted into the LSbit of the selected frame
size set in the SPILEN field. When LSBIT_1ST = 1, the LSbit of the selected frame size is sent
first, and the received data will be shifted into the MSbit of SPIDATA3.
Data returning from the SPI target will normally have its most significant data in the SPIDATA3
register. An exception will occur when LSBIT_1ST = 1 to indicate a right-shift transaction. In
this case the most significant byte of an 8-bit transaction will be located in SPIDATA0, a 16-bit
transaction's most significant byte will be located in SPIDATA1, and a 24-bit transaction's most
significant byte will be located in SPIDATA2.
EBX-37 Reference Manual
D6 D5 D4
D6 D5 D4
D6 D5 D4
D6 D5 D4
Interfaces and Connectors
D3 D2 D1
D3 D2 D1
D3 D2 D1
D3 D2 D1
D0
LSbit
D0
LSbit
D0
LSbit
D0
LSbit
52