VersaLogic VL-EBX-37 Reference Manual page 31

Intel core 2 duo sbc with video, ethernet, usb, serial, sata, audio, analog + digital i / o, pcie mini card, eusb, and spx
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outp( SIOINDEX,
outp( SIODATA,
outp( SIOINDEX,
baseIOHigh
= inp(
outp( SIOINDEX,
baseIOLow
= inp(
outp(
SIOINDEX, 0xAA
Bindex
=
(baseIOHigh
Bdata
=
Bindex
/*
Start Hardware Monitoring...
outp(
Bindex,
outp(
Bdata,
while
(keypressed
{
if
(kbhit())
{
keypressed
}
/*
Read FanTach1 LSB first, latches MSB.
outp( Bindex,
FTraw
= inp(
outp( Bindex,
FTraw
+= inp(
/* FTraw now contains the number of 90KHz pulses it took to find 5
tach edges. (5 edges = 2 tach pulses = 1 revolution)
/*
Convert Raw to RPMs...
RPM = 1 / (FTraw * 11.11uS / 2) * 60
fanRPM
=
FTraw
fanRPM
/= 2;
fanRPM
= 1/fanRPM;
_settextposition(4,1);
if
(
fanRPM
{
printf
(
delay(100);
}
else
{
printf
(
delay(100);
}
}
exit
(
0
);
}
EBX-37 Reference Manual
0x07
);
0x0A
);
0x60
);
SIODATA
);
0x61
);
SIODATA
) + RTOFFSET;
);
<< 8) + baseIOLow;
+ 1;
RLSREG
);
inp(
Bdata
) |
START
);
!= ESC)
=
getch();
FANTACHREG
);
Bdata
);
FANTACHREG
+
1
);
Bdata
) << 8;
* 0.00001111;
>
0
)
"FanTach 1: %5.0fRPMs
"FanTach 1: Stalled! \n"
//Point to Logical Device Config reg.
//Select SMSC Runtime reg.
//Index High Byte of Runtime reg base address.
//Read High Byte.
//Index Low Byte of Runtime reg base address.
//Read Low Byte and add offset to runtime reg base.
//Exit SIO Config mode
//Convert high and low bytes to 16-bit address.
//Index Ready, Lock, Start Reg.
//Set bit 0 to start.
//Fantach 1 LSB
//Fantach 1 MSB
\n",fanRPM*60
);
);
System Features
*/
*/
*/
*/
25

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