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WRITE ARRAY Sequence
The WRITE ARRAY sequence is similar to the WRITE BYTE sequence
unless more than one data byte is transferred. After the reception of every
data byte the internal destination address is auto-incremented by '1'. When
the highest address is reached (0x7FF in case of 2 kB RAM mode or
0xFFF in 4 kB mode), the address counter rolls over to address 0x000
allowing the write cycle to be continued indefinitely. The write operation is
terminated by raising the XSS pin.
XSS
0
1
2
SCK
(CPOL='0')
MOSI
0
0
0
MISO
XSS
32
33
34
SCK
(CPOL='0')
MOSI
7
6
5
MISO
Figure 8-10: WRITE ARRAY Sequence
8.1.4
I2C Interface Mode
The VPC3+S supports a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is defined as transmitter,
while a device receiving data is defined as a receiver. The bus has to be
controlled by a master device which generates the Serial Clock (SCK),
controls the bus access and generates the Start and Stop conditions, while
the VPC3+S works as slave. Both master and slave can operate as
transmitter or receiver, but the master device determines which mode is
activated.
The data on the SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only change when the
clock signal on the SCK line is LOW (Figure 8-11). One clock pulse is
generated for each data bit transferred.
VPC3+S User Manual
Copyright © profichip GmbH, 2012
3
4
5
6
7
8
9
Instruction
0
0
0
1
0
15
14
High-Impedance
35
36
37
38
39
40
41
Data Byte 2
4
3
2
1
0
7
6
High-Impedance
Revision 1.04
10
11
20
21
22
16-bit Address
13
12
3
2
1
42
43
44
45
46
47
Data Byte 3
5
4
3
2
1
0
Hardware Interface 8
23
24
25
26
27
28
29
Data Byte 1
0
7
6
5
4
3
2
Data Byte n
7
6
5
4
3
2
30
31
1
0
1
0
97
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