Timing In Spi Interface Mode - Profichip VPC3+S User Manual

10.6.6 Timing in SPI Interface Mode

XSS
SCK
(CPOL=0)
SCK
(CPOL=1)
HIGH IMPEDANCE
MISO
MOSI
Figure 10-20: Timing Diagram SPI Interface Mode (CPHA='0')
XSS
SCK
(CPOL=0)
SCK
(CPOL=1)
HIGH IMPEDANCE
MISO
MOSI
Figure 10-21: Timing Diagram SPI Interface Mode (CPHA='1')
VPC3+S User Manual
Copyright © profichip GmbH, 2012
t
t
S.XSS
HIGH.SCK
t t
S.SI
H.SI
VALID IN
t
t
S.XSS
HIGH.SCK
t
V.SO
t
S.SI
VALID IN
Revision 1.04
Operational Specifications 10
t
LOW.SCK
t
V.SO
VALID OUT
t
LOW.SCK
t
H.SO
VALID OUT
t
H.SI
t
HIGH.XSS
t t
H.SO DIS.SO
HIGH IMP.
t
HIGH.XSS
t
DIS.SO
HIGH IMP.
123