Mode Register 1 - Profichip VPC3+S User Manual

bit 15
rw-0
bit 14
rw-0
bit 13
rw-0
bit 12
rw-0
bit 11
rw-0
bit 10
rw-0
bit 9
rw-0
bit 8
rw-0
Figure 5-2: Coding of Mode Register 0, High-Byte
5.1.2

Mode Register 1

Some control bits must be changed during operation. These control bits are
combined in Mode Register 1 and can be set independently of each other
(Mode-Reg_1_S) or can be reset independently of each other (Mode-
Reg_1_R). Separate addresses are used for setting and resetting. A logical
'1' must be written to the bit position to be set or reset.
For example, to set START_VPC3 write a '1' to address 08H, in order to
reset this bit, write a '1' to address 09H.
VPC3+S User Manual
Copyright © profichip GmbH, 2012
Mode Register 0, High-Byte, Address 07H (Intel):
Reserved
PrmCmd_Supported: PrmCmd support for redundancy
0 = PrmCmd is not supported.
1 = PrmCmd is supported
Spec_Clear_Mode: Special Clear Mode (Fail Safe Mode)
0 = No special clear mode.
1 = Special clear mode. VPC3+S will accept data telegrams with data unit = 0
Spec_Prm_Buf_Mode: Special-Parameter-Buffer Mode
0 = No Special-Parameter-Buffer.
1 = Special-Parameter-Buffer mode. Parameterization data will be stored
directly in the Special-Parameter-Buffer.
Set_Ext_Prm_Supported: Set_Ext_Prm telegram support
0 = SAP 53 is deactivated
1 = SAP 53 is activated
User_Time_Base: Timebase of the cyclical User_Time_Clock-Interrupt
0 = The User_Time_Clock-Interrupt occurs every 1 ms.
1 = The User_Time_Clock-Interrupt occurs every 10 ms.
EOI_Time_Base: End-of-Interrupt Timebase
0 = The interrupt inactive time is at least 1 µs long.
1 = The interrupt inactive time is at least 1 ms long
DP_Mode: DP_Mode enable
0 = DP_Mode is disabled.
1 = DP_Mode is enabled. VPC3+S sets up all DP_SAPs (default configuration!)
Revision 1.04
ASIC Interface 5
27