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10.6 Timing Characteristics
All signals beginning with 'X' are 'low active'. All timing values are based on
the capacitive loads specified in the table above.
10.6.1 System Bus Interface
Clock
Clock frequency is 48 MHz. Distortion of the clock signal is permissible up
to a ratio of 30:70 at the threshold levels 0.9 V and 2.1 V.
Parameter
Clock period
Clock high time
Clock low time
Clock rise time
Clock fall time
Figure 10-6: Clock Timing
Note:
The VPC3+S is equipped with 5V tolerant inputs.
Interrupt:
After acknowledging an interrupt with EOI, the interrupt output of the
VPC3+S is deactivated for at least 1 us or 1 ms depending on the bit
EOI_Time_Base in Mode Register 0.
Parameter
Interrupt inactive time EOI_Timebase = '0'
Interrupt inactive time EOI_Timebase = '1'
Figure 10-7: End-of-Interrupt Timing
Reset:
VPC3+S requires a minimum reset phase of 100 ns at power-on.
VPC3+S User Manual
Copyright © profichip GmbH, 2012
Operational Specifications 10
Symbol
T
T
CH
T
CL
T
CR
T
CF
Revision 1.04
MIN
MAX
20.83
20.83
6.25
14.6
6.25
14.6
4
4
MIN
MAX
1
1
1
1
Unit
ns
ns
ns
ns
Unit
µs
ms
113
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