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8.1
Universal Processor Bus Interface
8.1.1
Overview
The VPC3+S can be interfaced by using either a parallel 8-bit data interface
or an SPI or I2C interface.
In parallel mode the VPC3+S provides an 8-bit data interface with an 11-bit
address bus. The VPC3+S supports all 8-bit processors and micro-
controllers based on the 80C51/52 (80C32) from Intel, the Motorola HC11
family, as well as 8- /16-bit processors or microcontrollers from the
Siemens 80C166 family, X86 from Intel and the HC16 and HC916 family
from Motorola. Because the data formats from Intel and Motorola are
different, VPC3+S automatically carries out 'byte swapping' for accesses to
the following 16-bit registers (Interrupt Register, Status Register and Mode
Register 0) and the 16-bit RAM cell (R_User_WD_Value). This makes it
possible for a Motorola processor to read the 16-bit value correctly.
Reading or writing takes place, as usual, through two accesses (8-bit data
bus).
Four SPI modes are supported which differ in clock polarity and clock
phase. In these interface modes the VPC3+S acts like a memory device
with serial (SPI) interface connected to the CPU. The chip needs to be
selected by pulling the Slave-Select pin (SPI_XSS) low before receiving
clock pulses via SPI_SCK pin from the CPU. Depending on the OP-code
received the VPC3+S carries out a read or write operation starting at the
specified address inside the internal memory. Serial data is shifted in via
SPI_MOSI pin and shifted out via SPI_MISO pin.
In I2C mode the VPC3+S can be connected to an I2C network by using the
pins I2C_SCK and I2C_SDA. In this mode the VPC3+S acts like a memory
device with serial (I2C) interface connected to the CPU. The chip supports
slave mode only and the desired slave address can be selected by using
the pins I2C_A[6:0]. Upon reception of the correct slave address and
depending on the status of the R/W bit the VPC3+S carries out a read or
write operation starting at the specified address inside the internal memory.
The Bus Interface Unit (BIU) and the Dual Port RAM Controller (DPC) that
controls accesses to the internal RAM belong to the processor interface of
the VPC3+S.
The VPC3+S is supplied with a clock pulse rate of 48MHz. In addition, a
clock divider is integrated. The clock pulse is divided by 2 (Pin: DIVIDER =
'1') or 4 (Pin: DIVIDER = '0') and applied to the pin CLKOUT. This allows
the connection of a slower controller without additional expenditures in a
low-cost application.
VPC3+S User Manual
Copyright © profichip GmbH, 2012
Hardware Interface
Revision 1.04
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8
Hardware Interface
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