Page 1 VPC3+S User Manual Revision 1.04...
Page 2 Required corrections are included in subsequent versions. We gratefully accept suggestions for improvements. Copyright Copyright © profichip GmbH 2009-2012. All Rights Reserved. Unless permission has been expressly granted, passing on this document or copying it, or using and sharing its content are not allowed.
Page 3: Table Of Contents
6.2.6 Global_Control (SAP 58) ..........56 6.2.7 RD_Input (SAP 56) ............57 6.2.8 RD_Output (SAP 57) ............. 57 6.2.9 Get_Cfg (SAP 59) ............58 7 PROFIBUS DP Extensions ........59 VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 4 10.6.7 Timing in I2C Interface Mode ........125 10.7 Package Specifications ............126 10.7.1 LFBGA48 ..............126 10.7.2 LQFP48 ............... 128 10.8 Processing Instructions ............130 10.9 Ordering Information ............... 130 Revision History ............133 Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 5: Introduction
Introduction Introduction Profichip’s VPC3+S is a communication chip with 8-Bit parallel processor interface for intelligent PROFIBUS DP-Slave applications. Alternatively an SPI or I C interface can be used to communicate with the chip. The VPC3+S handles the message and address identification, the data security sequences and the protocol processing for PROFIBUS DP.
Page 7: Functional Description
ARM derivates with parallel, SPI or I C interface The VPC3+S handles the physical layer 1 and the data link layer 2 of the ISO/OSI-reference-model excluding the analog RS485 drivers. The integrated 4K Byte Dual-Port-RAM serves as an interface between the VPC3+S and the software/application.
Page 8 Station_Address, etc.) and the data buffers. In the UART, the parallel data flow is converted into the serial data flow and vice-versa. The VPC3+S is capable of automatically identifying the baud rates (9.6 Kbit/s - 12 Mbit/s). The Idle Timer directly controls the bus times on the serial bus line.
Page 9: Pin Description
Pin Description Pin Description Pinout The VPC3+S is available in two package versions: LFBGA48 or LQFP48. Several pins are sharing different functions. Which pin function actually applies depends on the interface mode selected by the configuration pins. Four parallel interface modes as well as I2C and SPI mode with con- figurable clock phase and clock polarity are supported.
Page 10 XCTS AB5 / I2C_SA5 XREADY / DTACK /SPI_MISO / I2C_SDA AB8 / SPI_SCK / I2C_SCK Figure 3-2: VPC3+S LQFP48 Pinout (TOP VIEW) Details about package outlines and dimensions are listed in section 10.7. Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 11: Pin Assignment (Overview)
Configuration Pin ‘1’: 24 MHz ‘0’: Asynchronous Mode (Parallel Interface Mode) ‘1’: Synchronous Mode (Parallel Interface Mode) MODE Configuration Pin ‘0’: SPI (Serial Interface Mode) ‘1’: I2C (Serial Interface Mode) VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 12 +3.3 V GND = The assignment of AB11 depends on the parallel interface mode selected. All unused inputs must be connected to GND. Input Levels: LVTTL I (S) : LVTTL, Schmitt-Trigger Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 13: Asynchronous Intel Mode
Pin Description 3 The following chapters are describing the different processor interface modes supported by the VPC3+S. For every interface mode the settings of the configuration pins and the signals necessary to communicate with the microcontroller are listed. Common signals for all interface types (like clock divider, interrupt and Profibus interface signals are not explicitly listed in this overview.
Page 14: Synchronous Intel Mode
8 bit data bus DB[7:0]. The upper address lines (bits 10 to 8) need to be connected to the AB[2:0] inputs of the VPC3+S. Address line 11 is to be connected to pin C1 of the VPC3+S.
Page 15: Asynchronous Motorola Mode
In Asynchronous Motorola Mode the data and address busses are separate (non-multiplexed). When using HC11 types with a multiplexed bus the address signals AB[7:0] must be generated from the DB[7:0] signals externally. Address line 11 is to be connected to pin D5 of the VPC3+S. XDTACK mechanism is supported. Ball...
Page 16: Synchronous Motorola Mode
(non-multiplexed). When using HC11 types with a multiplexed bus the address signals AB[7:0] must be generated from the DB[7:0] signals externally. Address line 11 is to be connected to pin C5 of the VPC3+S. XDTACK mechanism is not supported. Ball...
Page 17: Spi Mode
I2C Mode The VPC3+S can be interfaced like an I2C compatible memory device. The VPC3+S is always in slave mode, master mode is not supported. The slave address can be configured by using the AB[6:0] inputs. All unused inputs (including DB[7:0]) must be connected to GND.
Page 19: Memory Organization
Data out means output data from DP-Master to DP-Slave Number of buffers depends on the entries in the SAP-List **** DXB out means input data from another DP-Slave (slave-to-slave communication) VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 20 4 Memory Organization Internal VPC3+S RAM (2K/4K Byte) Segment 0 Segment 1 Segment 2 8/16 bit segment addresses (pointer to the buffers) Segment 254 Segment 255 Building of the physical buffer address: 2K Byte Mode: Segment base address (8 bit)
Page 21: Control Parameters (Latches/Registers)
Control Parameters (Latches/Registers) These cells can be either read-only or write-only. In the Motorola Mode the VPC3+S carries out ‘address swapping’ for an access to the address locations 00H - 07H (word registers). That is, the VPC3+S internally generates an even address from an odd address and vice-versa.
Page 22 7..0 comparison with SYNCH telegram Group_Select value for comparison Group_Select_Reg 7..0 with SYNCH telegram Reserved Mode-Reg3 7..0 Mode Register 3 Reserved Figure 4-3: Assignment of the Internal Parameter-Latches for WRITE Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 23: Organizational Parameters (Ram)
These parameters can be written and read. Address Intel Mot. Name Bit No. Significance R_TS_Adr Setup Station_Address of the VPC3+S Pointer to a RAM address which is preset SAP_List_Ptr with FFh or to SAP-List R_User_WD_Value 7..0 In DP_Mode an internal 16-bit watchdog timer monitors the user.
Page 24 Register 0), this cell defines the length of the Prm_Buf. R_DXBout_Buf_Ptr2 Segment base address of DXBout_Buf 2 R_DXBout_Buf_Ptr3 Segment base address of DXBout_Buf 3 Figure 4-4: Assignment of the Organizational Parameters Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 25: Asic Interface
**) When a large number of parameters have to be transmitted from the DP-Master to the DP-Slave, the Aux-Buffer 1/2 must have the same length as the Parameter-Buffer. Sometimes this could reach the limit of the available memory in the VPC3+S. When Spec_Prm_Buf_Mode = 1 the parameterization data are processed directly in this special buffer and the Aux-Buffers can be held compact.
Page 26 1 = Monitoring the following start bit is switched off Set_Prm telegram overwrites this memory cell in the DP_Mode. (Refer to the user specific data.) Figure 5-1: Coding of Mode Register 0, Low-Byte Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 27: Mode Register 1
Spec_Clear_Mode: Special Clear Mode (Fail Safe Mode) bit 13 rw-0 0 = No special clear mode. 1 = Special clear mode. VPC3+S will accept data telegrams with data unit = 0 Spec_Prm_Buf_Mode: Special-Parameter-Buffer Mode bit 12 rw-0 0 = No Special-Parameter-Buffer.
Page 28 After this action, VPC3+ sets User_LEAVE-MASTER to ’0’ again. Go_Offline: Going into the Offline state bit 2 rw-0 1 = After the current request ends, VPC3+S goes to the Offline state and sets Go_Offline to ’0’ again. bit 1 EOI: End-of-Interrupt rw-0 1 = VPC3+S disables the interrupt output and sets EOI to ’0‘...
Page 29: Mode Register 2
Setting parameters for Mode Register 2 may take place in the Offline State only (like Mode Register 0). Bit Position Address Designation Reset Value Mode Reg 2 7 .. 0 VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 30 0 = New_GC_Command interrupt is only generated, if a changed Global_Control telegram is received 1 = New_GC_Command interrupt is generated after every Global_Control telegram (default) Figure 5-4: Coding of Mode Register 2 Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 31: Mode Register 3
0 = GC Interrupt is only generated, if changed GC telegram is received 1 = GC Interrupt is only generated, if GC telegram with changed Control_Command is received Figure 5-5: Coding of Mode Register 3 VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 32: Status Register
5 ASIC Interface Status Register The Status Register shows the current VPC3+S status and can be read only. Bit Position Address Designation Status-Reg WD_State DP_State (Intel) 7..0 See below for coding Bit Position Address Designation Status-Reg (Intel) VPC3+ Release Baud Rate 15..8...
Page 33 Figure 5-6: Status Register, Low-Byte Status Register, High-Byte, Address 05H (Intel): VPC3+-Release 3..0 : Release number for VPC3+ bit 15-12 r-1110 1110 Baud Rate 3..0 : The baud rate found by VPC3+S bit 11-8 r-1111 0000 = 12,00 Mbit/s 0001 =...
Page 34: Interrupt Controller
1 ms expires. This interrupt inactive time can be set via EOI_Time_Base in Mode Register 0. This makes it possible to enter the interrupt routine again when an edge-triggered interrupt input is used. Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 35: Interrupt Request Register
5.3.1 Interrupt Request Register Bit Position Address Designation Int-Req-Reg (Intel) 7 .. 0 See below for coding Bit Position Address Designation Int-Req-Reg (Intel) 15 .. 8 See below for coding VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 36 5 ASIC Interface Interrupt-Request-Register, Low-Byte, Address 00H (Intel): DXB_Out: bit 7 rw-0 VPC3+S has received a DXB telegram and made the new output data available in the ‘N’ buffer. New_Ext_Prm_Data: bit 6 rw-0 The VPC3+S has received a Set_Ext_Prm telegram and made the data available in the Parameter-Buffer.
Page 37 Due to the request made by New_Diag_Cmd, the VPC3+S exchanged the Diagnosis-Buffers and made the old buffer available to the user again. New_Prm_Data: bit 11 rw-0 The VPC3+S have received a Set_Prm telegram and made the data available in the Parameter-Buffer. New_Cfg_Data: bit 10 rw-0 The VPC3+S have received a Chk_Cfg telegram and made the data available in the Config-Buffer.
Page 38: Interrupt Acknowledge / Mask Register
User_Prm_Data_Okay etc.). Watchdog Timer The VPC3+S is able to identify the baud rate automatically. The state ma- chine is in the BAUD_SEARCH state after each RESET and also after the Watchdog (WD) Timer has expired in the BAUD_CONTROL state.
Page 39: Automatic Baud Rate Identification
ASIC Interface 5 5.4.1 Automatic Baud Rate Identification The VPC3+S starts searching for the transmission rate using the highest baud rate. If no SD1 telegram, SD2 telegram, or SD3 telegram was received completely and without errors during the monitoring time, the search continues using the next lower baud rate.
Page 40 5 ASIC Interface If the monitoring time expires, the VPC3+S goes to BAUD_CONTROL state again and generates the WD_DP_CONTROL_Timeout interrupt. In addition, the DP State Machine is reset, that is, it generates the reset states of the buffer management. This operation mode is recommended for the most applications.
Page 41: Profibus Dp Interface
PROFIBUS DP Extensions PROFIBUS DP Interface DP Buffer Structure The DP_Mode is enabled in the VPC3+S with ‘DP_Mode = 1’ (see Mode Register 0). In this mode, the following SAPs are permanently reserved: Default SAP: Write and Read data (Data_Exchange)
Page 42 Parameter- Buffer Figure 6-1: DP_SAP Buffer Structure The VPC3+S first stores the parameter telegrams (Set_Slave_Add and Set_(Ext_)Prm) and the configuration telegram (Chk_Cfg) in Aux-Buffer 1 or Aux-Buffer 2. If the telegrams are error-free, data is exchanged with the corresponding target buffer (Set_Slave_Add-Buffer, Parameter-Buffer and Config-Buffer).
Page 43 Aux-Buffer 2 available (R_Aux_Buf_Sel: Set_Prm = 1) for this telegram. The other telegrams are then read via Aux-Buffer 1 (R_Aux_Buf_Sel: Set_Slave_Adr = 0, Chk_Cfg = 0). If the buffers are too small, the VPC3+S responds with “no resources” (RR)! Bit Position...
Page 44: Description Of The Dp Services
R_TS_Adr und R_Real_No_Add_Change RAM registers. If SAP55 is enabled and the Set_Slave_Add telegram is received correctly, the VPC3+S enters the pure data in the Aux-Buffer 1/2, exchanges the Aux-Buffer 1/2 for the Set_Slave_Add-Buffer, stores the entered data length in R_Len_SSA_Data, generates the New_SSA_Data interrupt and internally stores the New_Slave_Add as Station_Address and the No_Add_Chg as Real_No_Add_Chg.
Page 45: Set _Prm (Sap 61)
User_Prm_Data), or the first eight data bytes (with User_Prm_Data). The first seven bytes are specified according to the standard. The eighth byte is used for VPC3+S specific characteristics. The additional bytes are available to the application. If a PROFIBUS DP extension shall be used, the bytes 7-9 are called DPV1_Status and must be coded as described in section 7, “PROFIBUS DP Extensions”.
Page 46 6 PROFIBUS DP Extensions Bit Position Byte Designation Station Status WD_Fact_1 WD_Fact_2 minT Ident_Number_High Ident_Number_Low Group_Ident Spec_User_Prm_Byte /DPV1_Status_1 DPV1_Status_2 DPV1_Status_3 User_Prm_Data Figure 6-5: Format of the Set_Prm Telegram Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 47 1 = Start bit monitoring in the receiver is disabled Figure 6-6: Spec_User_Prm_Byte / DPV1_Status_1 It is recommended not to use the DPV1_Status bytes (bytes 7-9) for user parameter data. VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 48 In the case of a positive validation of more than seven data bytes, the VPC3+S carries out the following reaction: The VPC3+S exchanges Aux-Buffer 1/2 (all data bytes are entered here) for the Parameter-Buffer, stores the input data length in R_Len_Prm_Data and triggers the New_Prm_Data interrupt.
Page 49: Chk_Cfg (Sap 62)
If another Set_Prm telegram is supposed to be received in the meantime, the signal Prm_Conflict is returned for the positive or negative acknowledgement of the first Set_Prm telegram. Then the user must repeat the validation because the VPC3+S has made a new Parameter-Buffer available. 6.2.3 Chk_Cfg (SAP 62) The user checks the correctness of the configuration data.
Page 50: Slave_Diag (Sap 60)
Cfg_Conflict signal during the positive or negative acknowledgement of the first Chk_Cfg telegram. Then the user must repeat the validation, because the VPC3+S have made a new Config-Buffer available. The User_Cfg_Data_Okay_Cmd and User_Cfg_Data_Not_Okay_Cmd acknowledgements are read accesses to defined memory cells with the relevant Not_Allowed, User_Cfg_Finished, or Cfg_Conflict signals.
Page 51 Figure 6-9: Diagnosis Buffer Assignment The New_Diag_Cmd is also a read access to a defined control parameter indicating which Diagnosis-Buffer belongs to the user after the exchange or whether both buffers are currently assigned to the VPC3+S (No_Buffer, Diag_Buf1, Diag_Buf2). VPC3+S User Manual Revision 1.04...
Page 52: Write_Read_Data / Data_Exchange (Default_Sap)
Write_Read_Data / Data_Exchange (Default_SAP) Writing Outputs The VPC3+S writes the received output data in the 'D' buffer. After an error- free receipt, the VPC3+S shifts the newly filled buffer from ‘D’ to ‘N'. In addition, the DX_Out interrupt is generated. The user now fetches the current output data from ‘N’.
Page 53 For power-on, LEAVE-MASTER and the Global_Control telegram with ‘Clear_Data = 1’, the VPC3+S deletes the ‘D’ buffer and then shifts it to ‘N'. This also takes place during power-up (entering the WAIT-PRM state). If the user fetches this buffer, he receives U_Buffer_Cleared during the Next_Dout_Buffer_Cmd.
Page 54 (cleared) data can be sent for a RD_Output telegram before the first data cycle. Reading Inputs The VPC3+S sends the input data from the ‘D’ buffer. Prior to sending, the VPC3+S fetches the Din-Buffer from ‘N’ to ‘D'. If no new buffer is present in ‘N', there is no change. user makes...
Page 55 PROFIBUS DP Extensions 6 During start-up, the VPC3+S does not go to DATA-EXCH before all parameter telegrams configuration telegrams have been acknowledged. If ‘Diag.Freeze_Mode = 1’, there is no buffer change prior to sending. The user can read the status of the state machine cell with the following codings for the four states: Nil, Dout_Buf_Ptr1, Dout_Buf_Ptr2 and Dout_Buf_Ptr3.
Page 56: Global_Control (Sap 58)
The interrupt behavior regarding to the reception of a Global_Control telegram can be configured via bit 8 of Mode Register 2. The VPC3+S either generates the New_GC_Control interrupt after each receipt of a Global_Control telegram (default) or just in case if the Global_Control differs from the previous one.
Page 57: Rd_Input (Sap 56)
6.2.8 RD_Output (SAP 57) The VPC3+S fetches the output data from the Dout_Buffer in ‘U’. The user must preset the output data with ‘0’ during start-up so that no invalid data can be sent here. If there is a buffer change from ‘N’ to ‘U’ (through the VPC3+S User Manual Revision 1.04...
Page 58: Get_Cfg (Sap 59)
Config-Buffer, sets ‘En_Change_Cfg_buffer = 1’ (see Mode Register 1) and the VPC3+S then exchanges the Config-Buffer for the Read_Config-Buffer. If there is a change in the configuration data during operation (for example, for a modular DP systems), the user must return with Go_Offline command (see Mode Register 1) to WAIT-PRM.
Page 59: Profibus Dp Extensions
If the DP-Slave requires Fail_Safe but the DP-Master doesn’t the Prm_Fault bit is set. If the VPC3+S should be used for DXB, IsoM or redundancy mode, the parameterization data must be packed in a Structured_Prm_Data block to distinguish between the User_Prm_Data. The bit Prm_Structure indicates this.
Page 60: Profibus Dp-V1
PROFIBUS DP-V1 7.2.1 Acyclic Communication Relationships The VPC3+S supports acyclic communication as described in the DP-V1 specification. Therefore a memory area is required which contains all SAPs needed for the communication. The user must do the initialization of this area (SAP-List) in Offline state. Each entry in the SAP-List consists of 7 bytes.
Page 61 SAP_Number: 0 – 51 Byte 1 Request_SA: The source address of a request is compared with this value. At differences, the VPC3+S response with “no service activated” (RS). The default value for this entry is 7FH. Byte 2 Request_SSAP: The source SAP of a request is compared with this value. At differences, the VPC3+S response with “no service activated”...
Page 62 (RS) or if no free buffer is available with “no resource” (RR). After finishing the processing of the incoming telegram, the INUSE bit is reset and the bits USER and IND are set by VPC3+S. Now the FDL_Ind interrupt is generated. Polling telegrams do not produce interrupts. The RESP bit indicates response data, provided by the user in the Response- Buffer.
Page 63: Diagnosis Model
Poll_End_Ind interrupt clear Poll_End_Ind interrupt search for SAP with Response_Sent = 1 clear Response_Sent Figure 7-6: FDL-Interface of VPC3+S (e.g. same Buffer for Indication and Response) 7.2.2 Diagnosis Model The format of the device related diagnosis data depends on the GSD keyword DPV1_Slave in the GSD.
Page 64: Profibus Dp-V2
DXBout DP-Slave (Subscriber) DP-Slave (Publisher) Link Figure 7-7 : Overview DXB The VPC3+S can handle a maximum of 29 links simultaneously. Publisher A Publisher is activated with 'Publisher_Enable = 1' in DPV1_Status_1. The time minT must be set to 'T...
Page 65 Bit Position Byte Designation Structured_Length Structure_Type Slot_Number Reserved Version Publisher_Addr Publisher_Length Sample_Offset Sample_Length further link entries Figure 7-8: Format of the Structured_Prm_Data with DXB Linktable (specific link is grey scaled) VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 66 DXB_Link_Buf and set R_Len_DXB_Link_Buf. Also the user must enter the default status message in DXB_Status_Buf with the received links and write the appropriate values to R_Len_DXB_Status_Buf. After that, the parameterization interrupt can be acknowledged. Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 67 The VPC3+S processes DXBout-Buffers like the Dout-Buffers. The only difference is that the DXBout-Buffers are not cleared by the VPC3+S. The VPC3+S writes the received and filtered broadcast data in the 'D' buffer. The buffer contains also the Publisher_Address and the Sample_Length.
Page 68 01 = DXBout_Buf_Ptr1 10 = DXBout_Buf_Ptr2 11 = DXBout_Buf_Ptr3 bit 1-0 D: Assignment of the D-Buffer 00 = Nil 01 = DXBout_Buf_Ptr1 10 = DXBout_Buf_Ptr2 11 = DXBout_Buf_Ptr3 Figure 7-12: DXBout-Buffer Management Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 69 In state DATA-EXCH the links are monitored in intervals defined by the parameterized watchdog time. After the monitoring time runs out, the VPC3+S evaluates the Link_Status of each Publisher and updates the bit Link_Status. The timer restarts again automatically. Link_...
Page 70: Isom (Isochronous Mode)
SYNCH telegram by the IsoM master. If the IsoM support of the VPC3+S is enabled, a synchroniza- tion signal at Pin C4 (SYNC) is generated by each reception of a SYNCH telegram.
Page 71 Isochronous Mode To enable the Isochronous Mode in the VPC3+S, bit SYNC_Ena in Mode Register 2 must be set. Additionally the Spec_Clear_Mode in Mode Register 0 must be set. The polarity of the SYNC signal can be adjusted with the SYNC_Pol bit.
Page 72 7 PROFIBUS DP Extensions Bit Position Byte Designation Station_Status WD_Fact_1 WD_Fact_2 minT Ident_Number_High Ident_Number_Low Group_Ident DPV1_Status_1 DPV1_Status_2 DPV1_Status_3 User_Prm_Data Figure 7-18: Format of Set_Prm telegram for IsoM Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 73 DX_Out in the IMR is set. Since the synchronization signal is now the DX_Out interrupt, it remains active until the interrupt is acknowledged. VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 74: Isom-Pll
In_Clock_Detect Figure 7-20: SYNC clock and status signals of PLL To enable the IsoM-PLL in the VPC3+S, bit PLL_Supported in Mode Register 3 must be set and the IsoM must be parameterized. A Structured_Prm_Data block for IsoM in the parameter telegram contains the configuration values for the PLL.
Page 75 Global_Control clock input clock display SYNC clock designated for actual value acquisition output clock display SYNC clock designated for setpoint transfer Figure 7-21: Inputs and outputs of the PLL VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 76 Figure 7-22: Format of Structured_Prm_Data with IsoM Parameter The following input parameters have to be calculated by firmware: SYNC cycle time: SYNC Number SYNC start value of PLL window: First Window with 0003 Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 77 Number_of_SYNC Number_of_SYNC(7:0) First_Window 1..(2 (Time Base reserved (9:8) PLL_I PLL_I Input_Time (7:0) (Time Base T PLL_I SYNC reserved (9:8) PLL_O PLL_O Output_Time (7:0) (Time Base T PLL_O SYNC 0..255 E_limit VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 78 0 = generate no SYNC signal at T 1 = generate SYNC signal at T Enable_In_Clock Enable_In_Clock: rw-0 0 = generate no SYNC signal at T 1 = generate SYNC signal at T Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 79 PLL_Start synchronization of PLL to GC clock → set hit display set Sync_Enable release clock on SYNC pin Figure 7-25: Start up of PLL (grey scaled task omitted if SYNC_Mode=0) VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 80: Cs (Clock Synchronization)
To achieve the most accuracy the receive delay timer is running until the user reads the Clock_Sync-Buffer. The VPC3+S only synchronizes the received telegrams, the system time management is done by the user. The user has also to account for the time...
Page 81 Clock_Sync_Interval is locked until the next LEAVE-MASTER or a new parameterization occurs. In addition it can be unlocked if the user set the Stop_Clock_Sync in Command byte. VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 82 Further information is contained in the Status byte. If an overflow of the Receive_Delay_Timer occurs the Status byte will be cleared. The VPC3+S cannot write new data to the Clock_Sync-Buffer until the user has acknowledged the Clock_Sync interrupt. Hence to ensure no new data overwrites the buffer, the user should read out the buffer before acknowledging the interrupt.
Page 83 7 1 = substract correction value to Time CV: Correction Value Clock_Value_ Status1 0 = 0 min bit 6-2 1..31 = 30..930 min r-00000 Clock_Value_ Reserved Status1 bit 1-0 r-00 VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 84 Intel format. rw-0 Clock_Sync_Interval: Value is stored with the most significant byte in address 24. No address swapping is done for Intel format. Figure 7-29: Format of the Clock_Sync-Buffer Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 85 Time_Event start Receive_Delay_Timer reception of Clock_Value set Clock_Sync interrupt read CS_Status IF (Set_Time=’1’) THEN stop Receive_Delay Timer read CS_Buffer update system time END IF acknowledge interrupt Figure 7-30: communication scheme VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 87: Hardware Interface
Serial data is shifted in via SPI_MOSI pin and shifted out via SPI_MISO pin. In I2C mode the VPC3+S can be connected to an I2C network by using the pins I2C_SCK and I2C_SDA. In this mode the VPC3+S acts like a memory device with serial (I2C) interface connected to the CPU.
Page 88: Parallel Interface Modes
The internal address latch and the integrated decoder must be used in the synchronous Intel mode. One figure shows the minimum con- figuration of a system with the VPC3+S, where the chip is connected to an EPROM version of the controller. Only a clock generator is necessary as an additional device in this configuration.
Page 89 The lower address bits AB7..0 are stored with the ALE signal in an in- ternal address latch.  The internal CS decoder is activated. VPC3+S generates its own CS signal from the address lines AB10..3. The VPC3+S selects the relevant address window from the AB2..0 signals.
Page 90  If the CPU is clocked by the VPC3+S, the output clock pulse (CLKOUT 2/4) must be 4 times larger than the E_Clock. That is, a clock pulse sig- nal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse (E_Clock).
Page 91: Spi Interface Mode
Hardware Interface 8 8.1.3 SPI Interface Mode The VPC3+S is designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed to match the SPI protocol.
Page 92 (CPOL=’0’) (CPOL=’1’) SAMPLE MOSI / MISO MOSI MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 8-4: SPI Transfer Format (CPHA='0') Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 93 (CPOL=’0’) (CPOL=’1’) SAMPLE MOSI / MISO MOSI MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 8-5: SPI Transfer Format (CPHA='1') VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 94 Register after the last bit is shifted in. Principles of Operation The VPC3+S contains an 8-bit instruction register and a 16-bit address register. The device is accessed via the MOSI pin, with data being clocked in on the configured edge of SCK. The XSS pin must be held low for the entire operation.
Page 95 The device is selected by pulling XSS low. The 8-bit READ BYTE instruc- tion is transmitted to the VPC3+S followed by the 16-bit address, with the four MSBs of the address being “don’t care” bits (in case of 2 kB RAM mode the five MSBs of the address are “don’t care”).
Page 96 Figure 8-8: READ ARRAY Sequence WRITE BYTE Sequence The VPC3+S is selected by pulling XSS low. The 8-bit WRITE BYTE instruction is transmitted to the device followed by the 16-bit address, with the four MSBs of the address being “don’t care” bits (in case of 2 kB RAM mode the five MSBs of the address are “don’t care”).
Page 97: I2C Interface Mode
Serial Clock (SCK), controls the bus access and generates the Start and Stop conditions, while the VPC3+S works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
Page 98 START or clock line held LOW STOP or byte complete, repeated START while interrupts are serviced repeated START interrupt within slave condition condition Figure 8-13: Data Transfer on the I2C Bus Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 99 SDA line checking the control byte transmitted and, upon receiving appropriate Slave Address bits, the device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the VPC3+S will select a read or write operation.
Page 100 ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the VPC3+S issues an acknowledge and transmits the 8-bit data byte. The master will not acknowledge the transfer, but does generate a STOP condition and the VPC3+S discontinues transmission.
Page 101 Address Pointer is set. The master issues the control byte again, but with the R/W bit set to a ‘1’. The VPC3+S will then issue an acknowledge and transmit the 8-bit data byte. The master will not acknowledge the transfer, but does generate a Stop condition which causes the VPC3+S to discontinue transmission (Figure 8-17).
Page 103: Application Examples (Principles)
Por t 2 PSEN AB 15..0 AB10 VPC3+ Reset Reset Mode Address- EPROM Decoder 3K 3 64kB 32kB 1K 1K RD W R Figure 8-21: 80C32 System with External Memory VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 104 DB 15..0 (82288) + 82244 VPC3+ AB(10..0) AB 12..1 AB 23..0 VPC3+ Reset Reset driver, control logic Mode CSRAM address EPROM CSEPROM decoder 64kB 32kB Figure 8-22: 80286 System (X86 Mode) Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 105: Application With 80C32 (2K Byte Ram Mode)
Figure 8-23: 80C32 Application in 2K Byte mode The internal chipselect is activated when the address inputs AB[10..3] of the VPC3+S are set to '0'. In the example above the start address of the VPC3+S is set to 1000H. Processor VPC3+ B DB[7..0]...
Page 106: Application With 80C32 (4K Byte Ram Mode)
Figure 8-25: 80C32 Application in 4K Byte mode The internal chipselect is activated when the address inputs AB[10..3] of the VPC3+S are set to '0'. In the example above the start address of the VPC3+S is set to 2000H. Processor VPC3+ B DB[7..0]...
Page 107: Application With 80C165
AB(10..0) Figure 8-27: 80C165 Application Dual Port RAM Controller The internal 4K Byte RAM of the VPC3+S is a single-port RAM. An integrated Dual-Port RAM controller, however, permits an almost simultaneous access of both ports (bus interface and microsequencer interface). When there is a simultaneous access of both ports, the bus interface has priority.
Page 108: Uart
(not in the target hardware environment!). Name Value Function All outputs high-resistance XTEST0 Normal VPC3+ function Various test modes XTEST1 Normal VPC3+ function Figure 8-28: Test Ports Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 109: Profibus Interface
PROFIBUS Interface PROFIBUS Interface Pin Assignment The data transmission is performed in RS485 operating mode (i.e., physical RS485). The VPC3+S is connected via the following signals to the galvanically isolated interface drivers. Signal Name Input/Output Function Output Request to send...
Page 110: Example For The Rs485 Interface
To minimize the capacity of the bus lines the user should avoid additional capacities. The typical capacity of a bus station should be 15...25 pF. Figure 9-2: Example for the RS485 Interface Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 111: Operational Specifications
µA Tri-state leakage current µA Current consumption (3.3V) Input capacitance Output capacitance Bi-directional buffer capacitance Θ Thermal Resist. (BGA48) 43.6 Θ Thermal Resist. (QFP48) 72.2 Figure 10-3: General DC Characteristics VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 112: Ratings For The Output Drivers
Output current LOW level, 8mA cell Output current HIGH level, 8mA cell Figure 10-5: DC Specification of I/O Drivers for 3.3V Operation Notes: The VPC3+S is equipped with 5V tolerant inputs. Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 113: Timing Characteristics
The VPC3+S is equipped with 5V tolerant inputs. Interrupt: After acknowledging an interrupt with EOI, the interrupt output of the VPC3+S is deactivated for at least 1 us or 1 ms depending on the bit EOI_Time_Base in Mode Register 0. Parameter Unit Interrupt inactive time EOI_Timebase = ‘0’...
Page 114: Timing In The Synchronous Intel Mode
An internal chipselect signal is generated from the most significant address bits. The request for an access to the VPC3+S is generated from the falling edge of the read signal (XRD) and from the rising edge of the write signal (XWR).
Page 115 (AB7..0) holdtime after XRD/XWR data holdtime after XRD XRD / XWR cycletime to XWR XWR pulsewidth data setuptime to XWR to ALE data holdtime after XWR Figure 10-10: Timing, Synchronous Intel Mode VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 116: Timing In The Asynchronous Intel Mode
In the asynchronous Intel mode, the VPC3+S acts like a memory with ready logic. The access time depends on the type of access. The request for an access to the VPC3+S is generated from the falling edge of the read signal (XRD) or the rising edge of the write signal (XWR).
Page 117 XCS holdtime after XRD / XWR XREADY holdtime after XRD / XWR data setuptime to XWR XWR pulsewidth data holdtime after XWR Figure 10-13: Timing, Asynchronous Intel Mode VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 118: Timing In The Synchronous Motorola Mode
10 Operational Specifications 10.6.4 Timing in the Synchronous Motorola Mode If the CPU is clocked by the VPC3+S, the output clock pulse (CLKOUT 2/4) must be 4 times larger than the E_Clock. That is, a clock pulse signal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse (E_Clock).
Page 119 R_W setuptime to E_Clock R_W holdtime after E_Clock XCS setuptime to E_Clock XCS holdtime after E_Clock Data setuptime to E_Clock Data holdtime after E_Clock Figure 10-16: Timing, Synchronous Motorola Mode VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 120: Timing In The Asynchronous Motorola Mode
Ready logic, whereby the access times depend on the type of access. The request for an access of the VPC3+S is generated from the falling edge of the AS signal (in addition: XCS = '0', R_W = '1'). The request for a write access is generated from the rising edge of the AS signal (in addition: XCS = '0', R_W = '0').
Page 121 Operational Specifications 10 AB10..0 valid DB7..0 data valid XDTACK (normal) XDTACK (early) Figure 10-18: Asynchronous Motorola Mode (WRITE) VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 122 R_W holdtime after AS XCS holdtime after AS XDTACK holdtime after AS Data setuptime to AS AS pulsewidth (write access) Data holdtime after AS Figure 10-19: Timing, Asynchronous Motorola Mode Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 123: Timing In Spi Interface Mode
Figure 10-20: Timing Diagram SPI Interface Mode (CPHA='0') HIGH.XSS S.XSS HIGH.SCK LOW.SCK (CPOL=0) (CPOL=1) V.SO H.SO DIS.SO HIGH IMPEDANCE HIGH IMP. MISO VALID OUT S.SI H.SI MOSI VALID IN Figure 10-21: Timing Diagram SPI Interface Mode (CPHA='1') VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 124 Data Out Hold Time H.SO Data In Set-up Time S.SI Data In Hold Time H.SI Output Disable Time DIS.SO XSS Inactive (High) Time HIGH.XSS Figure 10-22: Timing, SPI Interface Mode Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 125: Timing In I2C Interface Mode
Start Condition Set-up Time S.STA Data In Hold Time H.DAT Data In Set-up Time S.DAT Stop Condition Set-up Time S.STO Data Out Hold Time Figure 10-24: Timing, I2C Interface Mode VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 126: Package Specifications
10 Operational Specifications 10.7 Package Specifications 10.7.1 LFBGA48 Figure 10-25: LFBGA48 Package Drawing Revision 1.04 VPC3+S User Manual Copyright © profichip GmbH, 2012...
Page 129 0.50 BSC 0.45 0.60 0.75 1.00 REF 0.08 0.08 0.20 0.20 Θ 0° 3.5° 7° Θ 0° Θ 12° TYP Θ 12° TYP Figure 10-28 : LQFP48 Package Dimensions and Tolerances VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
Page 130: Processing Instructions
Profichip products are tested and classified for moisture sensitivity according to the procedures outlined by JEDEC. The VPC3+S is classified as moisture sensitivity level (MSL) 3. In order to minimize any potential risk caused by moisture trapped inside non-hermetic packages it is a general recommendation to perform a drying process before soldering.
Page 131: Revision History
Timing table for I2C interface mode corrected (MIN/MAX values swapped) V1.04 10.10.2012 10-17 Pin assignment of LQFP48 package version added Thermal resistance of LQFP48 package added 128-129 LQFP48 package drawing added Processing instructions revised and ordering information added VPC3+S User Manual Revision 1.04 Copyright © profichip GmbH, 2012...
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Profichip VPC3+S User Manual

1 Introduction

2 Functional Description

3 Pin Description

4 Memory Organization

5 ASIC Interface

6 PROFIBUS DP Interface

7 PROFIBUS DP Extensions

8 Hardware Interface

9 PROFIBUS Interface

10 Operational Specifications

Revision History

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