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7 PROFIBUS DP Extensions
7.3.3
CS (Clock Synchronization)
The Clock Synchronization mechanism synchronizes the time between
devices on a PROFIBUS segment. A time master is a DP-Master. The
scheme used is a "backwards time based correction". The knowledge of
when a special timer event message was broadcasted is subsequently
used to calculate appropriate clock adjustments.
The synchronized time can be used for time stamp mechanism.
Time Master
Output
Time Receiver
Input
Time Receiver
Application
1: Time Event
2: Clock_Sync Interrupt
3: read access Receive_Delay_Time
4: update system timer
Figure 7-26: clock synchronization mechanism
The clock synchronization sequence consists of two messages broad-
casted by the time master. When the first message, called Time_Event, is
received the VPC3+S starts the receive delay timer (t
then sends a second message, called Clock_Value, which contains the
actual time when the Time_Event was sent plus the send delay time (t
By receiption of the second message the Clock_Sync interrupt will be
generated. To achieve the most accuracy the receive delay timer is running
until the user reads the Clock_Sync-Buffer.
The VPC3+S only synchronizes the received telegrams, the system time
management is done by the user. The user has also to account for the time
after the receive delay timer has been read till the update of the system
time (t
The time for transmission delay (t
Clock_Sync_Interval
Structured_Prm_Data block. The CS_Delay_Time is used by the user to
calculate the system time: t
80
Time_Event
Time_Event
t
t
SD
DT
1
: process delay time).
PD
are
Revision 1.04
Clock_Value
Clock_Value
t
RD
: CS_Delay_Time) and the
DT
communicated
to
= Clock_Value_Time_Event + t
S
Copyright © profichip GmbH, 2012
t
t
t
t
PD
2
3
4
). The time master
RD
SD
the
VPC3+S
by
+ t
+ t
DT
RD
PD
VPC3+S User Manual
).
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