Interrupt Acknowledge / Mask Register; Watchdog Timer - Profichip VPC3+S User Manual

5 ASIC Interface
5.3.2

Interrupt Acknowledge / Mask Register

The other interrupt controller registers are assigned in the bit positions like
the Interrupt Request Register.
Address
02H / 03H Interrupt
04H / 05H Interrupt
02H / 03H Interrupt
Figure 5-11: Interrupt Acknowledge / Mask Register
The
acknowledged via the Interrupt Acknowledge Register. The relevant state
machines clear these interrupts through the user acknowledgements (for
example, User_Prm_Data_Okay etc.).
5.4

Watchdog Timer

The VPC3+S is able to identify the baud rate automatically. The state ma-
chine is in the BAUD_SEARCH state after each RESET and also after the
Watchdog (WD) Timer has expired in the BAUD_CONTROL state.
WD_DP_CONTROL_Timeout
Figure 5-12: Watchdog State Machine (WD_SM)
38
Register
Readable only
Register (IR)
Writeable, can
Mask be changed
Register during operation
(IMR)
Writeable, can
Acknowledge be changed
Register during operation
(IAR)
New_(Ext_)Prm_Data,
BAUD_SEARCH
WD_Timeout
baudrate detected
BAUD_CONTROL
WD_On = 0
or
DP_CONTROL
Revision 1.04
Reset state
All bits
cleared
All bits set
All bits
cleared
New_Cfg_Data
WD_On = 1
Copyright © profichip GmbH, 2012
Assignment
1 = Mask is set and the
interrupt is disabled
0 = Mask is cleared and the
interrupt is enabled
1 = Interrupt is
acknowledged and the IRR
bit is cleared
0 = IRR bit remains
unchanged
interrupts cannot
VPC3+S User Manual
be