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7 PROFIBUS DP Extensions
7.3.2.1 IsoM-PLL
The PLL shall handle following issues:
GC_Clock_Hit
GC_Clock_Detect
GC_Clock_Detect
Out_Clock_Detect
In_Clock_Detect
Figure 7-20: SYNC clock and status signals of PLL
To enable the IsoM-PLL in the VPC3+S, bit PLL_Supported in Mode
Register 3 must be set and the IsoM must be parameterized. A
Structured_Prm_Data block for IsoM in the parameter telegram contains
the configuration values for the PLL.
74
The jitter of the SYNCH telegrams has to be smoothed by the PLL.
-
If the jitter exceeds a certain limit, the PLL will recognize a loss of
the synchronization.
SYNCH telegrams lost due to bus disturbances have to be
-
compensated.
Phase shifts due to line delay between the different DP-slaves may
-
be compensated.
Generation of a SYNC clock in every slave cycle. The slave
-
application cycle time must be an integer part of DP cycle time.
Reset
Global_Control clock
(T
)
DP
Jitter <= 1 us
Parameter
occurence of Global_Control
ok
DP-Cycle (T
)
DP
T
SYNC
SYNC
behaviour in case of: Enable_In_Clock=1, Enable_Out_Clock=1, Enable_GC_Clock=1
Number_of_SYNC=3, T
SYNC
Revision 1.04
PLL
error
ok
(delayed)
Sync_PW_Reg
=3, T
=2
PLL_I
PLL_O
Copyright © profichip GmbH, 2012
SYNC clock
(T
/n)
DP
Jitter <= 100 ns
Status
error
(missing)
t
tolerance window
VPC3+S User Manual
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