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8.1.5
Application Examples (Principles)
CLK
WR
RD
INT 0
Por t 0
80C 32/
C501
ALE
Por t 2
Reset
Figure 8-20: Low Cost System with 80C32
CLK
WR
RD
INT0
80C 32
20/16 MHz
ALE
A/D 7..0
Po rt 0
AB 15..8
Por t 2
PSEN
Reset
Figure 8-21: 80C32 System with External Memory
VPC3+S User Manual
Copyright © profichip GmbH, 2012
A / D 7 ...0
AB 1 5...8
Address-
Latch
AB 15..0
EPROM
RAM
64kB
32kB
RD W R
Revision 1.04
Hardware Interface 8
(0000 0XXX)
1K
1K 1K
GND
(0000 0XXX)
Address-
Decoder
1K
1K 1K
GND
Clock-Generator
48MHz
DIV IDE R
Clockdivider
XW R
XRD
RT S
X/INT
TxD
DB 7..0
Data
Rx D
DB 7..0
Address-Latch
XC TS
VPC3+
AB 7 ..0
1K
Decoder
GND
AB8
AB9
AB10
VPC3+
Reset
Mode
3K 3
VDD
Clock-Generator
48 MHz
DIVIDE R
Clockdivider
XW R
XRD
RT S
X/INT
TxD
DB 7..0
Data
Rx D
DB 7..0
XC TS
Address-Latch
VPC3+
1K
GND
AB8
AB9
AB10
VPC3+
Reset
Mode
3K 3
VDD
103
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