Table of Contents
Advertisement
8.1.6
Application with 80C32 (2K Byte RAM Mode)
µC
µC
µC
µC
AB(15..8)
µC
Figure 8-23: 80C32 Application in 2K Byte mode
The internal chipselect is activated when the address inputs AB[10..3] of
the VPC3+S are set to '0'.
In the example above the start address of the VPC3+S is set to 1000H.
Figure 8-24: Internal Chipselect Generation in Synchronous Intel Mode, 2K Byte RAM
VPC3+S User Manual
Copyright © profichip GmbH, 2012
VPC3+
5
CLK
48 MHz
8
GND
XINT/MOT
1K
36
RESET
1
VDD
3K3
XCS
23
VDD
MODE
3K3
24
ALE
2
XWR
XWR
XRD
4
XRD
34
XTEST0
3K3
VDD
35
XTEST1
VDD
3K3
3
connect to
DIVIDER
VDD or GND
AB8
44
AB0
AB9
43
AB1
AB10
41
AB2
AB11
40
AB3
AB12
37
1
AB4
AB13
42
AB5
AB14
32
AB6
AB15
31
AB7
29
AB8
1K
25
AB9
1K
10
GND
AB10
1K
Processor
ALE
8
AD[7..0]
3
AB[10..8]
5
AB[15..11]
Revision 1.04
Hardware Interface 8
7
CLK2
13
XDATAEX
14
XREADY
9
X/INT
33
XCTS
30
RXD
27
RTS
26
TXD
11
DB0
12
DB1
15
DB2
16
DB3
19
DB4
20
DB5
21
DB6
22
DB7
VPC3+ B
ALE
DB[7..0]
8
address
latch
AB[2..0]
internal address
AB[7..3]
8
CS
decoder
3
AB[10..8]
all bits
zero
LED for Data_Exchange
µC
GND
1K
RS485
RS485
RS485
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
µC
DB(7..0)
11
4.0 KB
RAM
1
internal chip
select
105
Advertisement
Table of Contents
