Synchronous Intel Mode - Profichip VPC3+S User Manual

3 Pin Description
3.2.2

Synchronous Intel Mode

In Synchronous Intel Mode the lower 8 bits of the address lines are
multiplexed with the 8 bit data bus DB[7:0]. The upper address lines (bits
10 to 8) need to be connected to the AB[2:0] inputs of the VPC3+S.
Address line 11 is to be connected to pin C1 of the VPC3+S.
XREADY mechanism is not supported in this interface mode.
Ball Pin
Signal Name
BGA QFP
E3 9 SERMODE
E4 28 MOT/XINT
D4 33 MODE
C1 3 AB11
A6 37 AB2
B5 39 AB1
B6 36 AB0
G4 20 DB7
H5 23 DB6
H6 24 DB5
G5 22 DB4
G6 25 DB3
F4 21 DB2
F6 27 DB1
F5 26 DB0
C2 2 AB10
B3 44 AB9
A1 48 AB8
B1 1 AB7
C3 45 AB6
B2 46 AB5
B4 41 AB4
A5 38 AB3
C5 35 ALE
D5 32 XWR
C6 34 XRD
Figure 3-5: Interface Configuration: Synchronous Intel Mode
14
In/Out Description
'0': Parallel Interface
I
'0': Intel Format
I
'1': Synchronous Interface Mode
I
I Address Bit 11
I Address Bit 10
I Address Bit 9
I Address Bit 8
IO
IO
IO
Data Bus [7:0]
IO
multiplexed with lower address bits [7:0]
IO
ALE used to latch the lower address bits.
IO
IO
IO
I
I
I(S)
In Synchronous Intel Mode these inputs are used to
I(S)
generate the internal Chip-Select signal.
I
Chip-Select is active if all inputs are '0'.
I
I
I
Address Latch Enable
I The lower address bits [7:0] are latched with the falling
edge of ALE
I Write Signal (active low)
I Read Signal (active low)
Revision 1.04
Connect to
GND
GND
VCC
CPU Address Bus 11
CPU Address Bus 10
CPU Address Bus 9
CPU Address Bus 8
CPU Data/Address
Bus [7:0]
Use one (inverted)
CPU Address Line for
generating the
VPC3+S Chip-Select
signal.
Connect all other
inputs to GND.
CPU ALE
CPU Write
CPU Read
VPC3+S User Manual
Copyright © profichip GmbH, 2012