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5 ASIC Interface
5.3
Interrupt Controller
The processor is informed about indication messages and various error
events via the interrupt controller. Up to a total of 16 events are stored in
the interrupt controller. The events are summed up to a common interrupt
output. The controller does not have a prioritization level and does not
provide an interrupt vector (not 8259A compatible!).
The controller consists of an Interrupt Request Register (IRR), an Interrupt
Mask Register (IMR), an Interrupt Register (IR) and an Interrupt Acknowl-
edge Register (IAR).
µP
Figure 5-8: Block Diagram of Interrupt Controller
Each event is stored in the IRR. Individual events can be suppressed via
the IMR. The input in the IRR is independent of the interrupt masks. Events
that are not masked in the IMR set the corresponding IR bit and generate
the X/INT interrupt via a sum network. The user can set each event in the
IRR for debugging.
Each interrupt event that was processed by the microcontroller must be
deleted via the IAR (except for New_(Ext_)Prm_Data and New_Cfg_Data).
A logical '1' must be written on the specific bit position. If a new event and
an acknowledge from the previous event are present at the IRR at the
same time, the event remains stored. If the microcontroller enables a mask
subsequently, it must be ensured that no prior IRR input is present. To be
on the safe side, the position in the IRR must be deleted prior to the
enabling of the mask.
Before leaving the interrupt routine, the microprocessor must set the 'end of
interrupt bit' (EOI = 1) in Mode Register 1. The interrupt output is switched
to inactive with this edge change. If another event occurs, the interrupt
output is not activated again until the interrupt inactive time of at least 1 µs
or 1 ms expires. This interrupt inactive time can be set via EOI_Time_Base
in Mode Register 0. This makes it possible to enter the interrupt routine
again when an edge-triggered interrupt input is used.
34
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VPC3+
S
µP
IRR
R
IAR
Revision 1.04
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µP
S
IMR
IR
R
INT_POL
Copyright © profichip GmbH, 2012
X/INT
VPC3+S User Manual
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