Table of Contents
Advertisement
The following chapters are describing the different processor interface modes supported by
the VPC3+S. For every interface mode the settings of the configuration pins and the signals
necessary to communicate with the microcontroller are listed. Common signals for all
interface types (like clock divider, interrupt and Profibus interface signals are not explicitly
listed in this overview.
3.2.1
Asynchronous Intel Mode
In Asynchronous Intel Mode the data and address busses are separate
(non-multiplexed). Address line 11 is to be connected to pin C5 of the
VPC3+S.
XREADY mechanism is supported.
Ball
Pin
Signal Name
BGA
QFP
E3
9
SERMODE
E4
28
MOT/XINT
D4
33
MODE
C5
35
AB11
C2
2
AB10
B3
44
AB9
A1
48
AB8
B1
1
AB7
C3
45
AB6
B2
46
AB5
B4
41
AB4
A5
38
AB3
A6
37
AB2
B5
39
AB1
B6
36
AB0
G4
20
DB7
H5
23
DB6
H6
24
DB5
G5
22
DB4
G6
25
DB3
F4
21
DB2
F6
27
DB1
F5
26
DB0
C1
3
XCS
D5
32
XWR
C6
34
XRD
Figure 3-4: Interface Configuration: Asynchronous Intel Mode
VPC3+S User Manual
Copyright © profichip GmbH, 2012
In/Out
Description
'0': Parallel Interface
I
'0': Intel Format
I
'0': Asynchronous Interface Mode
I
I
Address Lines Bit 11
I
I
I(S)
I(S)
I
I
Address Lines Bits [10:0]
I
I
I
I
I
IO
IO
IO
IO
Data Bus [7:0]
IO
IO
IO
IO
I
Chip-Select Signal (active low)
I
Write Signal (active low)
I
Read Signal (active low)
Revision 1.04
Pin Description 3
Connect to
GND
GND
GND
CPU Address Bus 11
CPU
Address Bus [10:0]
CPU Data Bus [7:0]
CPU Chip-Select
CPU Write
CPU Read
13
Advertisement
Table of Contents
