GE L60 Instruction Manual page 196

5.5 GROUPED ELEMENTS
In single phase comparison schemes, coincidence of the local and remote squares is detected during half the power cycle
only, positive or negative. As a result, some delay in operation can be expected under "unfavorable" fault inception. This
weakness of the single phase comparison schemes is eliminated in dual phase comparison schemes but cost of the com-
munication link is higher.
Some advantages of dual phase comparison and two frequency FSK PLC are incorporated in the unblocking scheme.
Since there is no third or guard frequency available, the PLC low frequency signal serves as the guard frequency for some
logic implemented in this scheme. Tripping is permitted if the FDL relay sees the change in received signal form low to high
5
(indicated that communication link is healthy and remote relay detected the fault) within 20 ms after fault is detected. If the
PLC low frequency has not being received prior the fault detection, the trip output is blocked as well. Another enhancement
of this scheme is the trip window defined by the
trip decision within this time if the PLC signal was lost in the course of the fault.
The phase comparison function can be used for three-terminal line protection and breaker-and-a-half configuration. The
feature combines the advantages of the modern digital relay with the traditional "analog principle" approach. Pulses
received from a PLC are digitally sampled at 64 samples per cycle, providing excellent resolution. This also eliminates car-
rier building-up and tailing-off problems, since the voltage threshold for received pulses is user-programmable. If a pulse
received from PLC is consciously distorted and is not equal to half of the sinewave, it can be adjusted with the
settings. All phase comparison signals are captured and available in oscillography for commissioning, trouble-
ASYMMETRY
shooting, and analysis purposes. The L60 features excellent stability during channel noise due to the high sampling rate of
the received signal, and the unique integrator makes the digital phase-comparison relay fully equivalent to analogue phase-
comparison relays.
The following figure illustrates the phase comparison logic. The choice of the scheme must made by protection and control
engineer according to the communication equipment employed, requirements of trip speed, and reliability. These schemes
are considered in Chapter 8: Theory of Operation.
SETTINGS
87PC FUNCTION:
Enable=1
87PC BLOCK:
AND
Off=0
SETTINGS
CHARGE CURRENT COMP:
Enable=1
CHARGE COMP BLOCK:
AND
Off=0
SETTING
87PC LINE XC0 & XC1:
87PC VOLTAGE SOURCE :
RUN
L5 PHASE VT BANK: VA
Compute Charging
L5 PHASE VT BANK: VB
Current
L5 PHASE VT BANK: VC
SETTING
87PC SIGNAL SOURCE :
ONE SOURCE CURRENT
F1 PHASE CT BANK: IA
F1 PHASE CT BANK: IB
F1 PHASE CT BANK: IC
TWO SOURCE CURRENT
L1 PHASE CT BANK: IA
I_2
L1 PHASE CT BANK: IB
L1 PHASE CT BANK: IC
SETTING
87PC CH1 RX VOLT:
L60 DSP CARD
87PC CH2 RX VOLT:
87PC Rx1P V1P > PICKUP
87PC Rx1N V1N > PICKUP
87PC Rx2P V2P > PICKUP
87PC Rx2N V2N > PICKUP
Channel 1-from carrier #1
Channel 2-from carrier #2
FLEXLOGIC OPERAND
Force Keying
OPEN BKR ECHO PKP
5-94
87PC CHNL LOSS TRIP WINDOW
SETTINGS
87PC SIGNAL: 87PC SCHEME SELECT:
(I_2-K*I_1 or 3*I_0)
2TL-TR-SPC-2FC etc
87PC FDH AUX:
87PC MIXED SIGNAL K:
87PC MIXED SIG REF ANG: 87PC SYMMETRY CH1:
87PC FDL PICKUP: 87PC SYMMETRY CH2:
87PC CH1 DELAY:
87PC FDL AUX:
87PC FDH PICKUP: 87PC CH2 DELAY:
RUN
87PC IOC FDL OP
87PC V2 FDL OP
BRK 1 FDL OP
87PC dI1/dt FDL OP OR
I_2-K*I_1 or 3*I_0
87PC dI2/dt FDL OP
MIXING NETWORK
87PC FDL AUX OP
87PC IOC FDH OP
BRK 2
87PC V2 FDH OP
FDH OP
I_2-K*I_1 or 3*I_0 87PC dI1/dt FDH OP
OR
87PC dI2/dt FDH OP
MIXING NETWORK
87PC FDH AUX OP
Positive Delayed Local Pulse
Rx1P Positive Adjusted Remote Pulse
Rx1N
Rx2P
Rx2N
Negative Delayed Local Pulse
Negative Adjusted Remote Pulse
87PC LOGIC
Figure 5–39: OVERALL PHASE COMPARISON LOGIC
L60 Line Phase Comparison Relay
setting. This logic allows the relay to make a
TRANSMIT LOGIC
SETTINGS
87PC CHNL LOSS TRIP
WINDOW:
87PC STABILITY ANGLE :
87PC ENHANCED STAB
ANGLE:
87PC TRIP SECURITY:
AND
SETTING
87PC SECOND COINCID
87PC RESET DELAY:
TIMER:
>T
ò dt
STAB. ANG.
0
Positive Half Integrator T
RST
OR
ò dt >T
AND
STAB. ANG.
Negative Half Integrator
5 SETTINGS
87PC CH1(2)
L60 DSP CARD
87PC Tx1P
87PC Tx2P
87PC Tx1N
87PC Tx2N
FLEXLOGIC OPERAND
87PC FDL OP
87PC FDH OP 87PC FDH OP
SETTINGS
87PC TRANS BLOCK:
FLEXLOGIC OPERAND
T
87PC TRANS BLOCK OP
PKP
T
AND RST
87PC PKP
87PC DPO
87PC OP
SETTING
87PC HIGH-SPEED
CONTACT 1:
Off
AND
SETTING
87PC HIGH-SPEED
CONTACT 2:
Off
831017AC.CDR
GE Multilin