Post Codes - EPOX EP-MVP3G-M User Manual

EP-MVP3G-M/2/5
B-1 POST CODES
ISA POST codes are typically output to I/O port address 80h.
POST (hex)
01-02
C0
03
04
05
06
07
08
C1
C5
08
09
0A
0B
DESCRIPTION
Reserved.
Turn off OEM specific cache, shadow.
1. Initialize EISA registers (EISA BIOS only).
2. Initialize all the standard devices with default values
Standard devices includes.
- DMA controller (8237).
- Programmable Interrupt Controller (8259).
- Programmable Interval Timer (8254).
- RTC chip.
Reserved
1. Keyboard Controller Self-Test.
2. Enable Keyboard Interface.
Reserved.
Verifies CMOS's basic R/W functionality.
Auto-detection of onboard DRAM & Cache.
Copy the BIOS from ROM into E0000-FFFFF shadow RAM
so that POST will go faster.
Test the first 256K DRAM.
OEM specific cache initialization. (if needed)
1. Initialize the first 32 interrupt vectors with correspond
ing Interrupt handlers. Initialize INT numbers from 33-120
with Dummy (Spurious) Interrupt Handler.
2. Issue CPUID instruction to identify CPU type.
3. Early Power Management initialization. (OEM specific)
1. Verify the RTC time is valid or not.
2. Detect bad battery.
3. Read CMOS data into BIOS stack area.
4. PnP initializations including. (PnP BIOS only)
- Assign CSN to PnP ISA card.
Appendix
Appendix B
A-5