EPOX EP-MVP3G-M User Manual page 36

BIOS
Reset Configuration Data: The default value is Disabled.
Disabled: Normal Setting
Enabled: If you plug some Legacuy cards in the system and record into
ESCD (Extended System Configuration Data). You can set this
field to be Enabled and to clear ESCD at one time, when some
Legacy cards are removed.
CPU to PCI Write Buffer: When enabled, up to four D words of data can be
written to the PCI bus without interruting the CPU. When disabled, a write buffer
is not used and the CPU read cycle will not be completed until the PCI bus signals
that it is ready to receive the data.
The Choice: Enabled, Disabled.
PCI Dynamic Bursting: When Enabled, data transfers on the PCI bus, where
possible, make use of the high-performance PCI bust protocol, in which graeater
amounts of data are transferred at a single command.
The Choice: Enabled, Disabled.
PCI Master 0 WS Write: When Enabled, writes to the PCI bus are command
with zero wait states.
The Choice: Enabled, Disabled.
PCI Delay Transaction: The chipset has an embedded 32-bit posted write buffer
to support delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
The Choice: Enabled, Disabled.
PCI #2 Access #1 Retry: This item allows you enabled/disable the PCI #2
Access #1 Retry.
The Choice: Enabled, Disabled.
Assign IRQ for USB: This item allows the BIOS to assign an IRQ to the USB
controller. If no USB devices are used in the system this can be set to "disabled" to
free an IRQ for other device uses. The default is Enabled.
Disabled: Release IRQ for other device.
Enabled: Release IRQ for other device.
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