Interface Signals - Intel Arria 10 series User Manual

Clock
2
I C Clock
Related Links
• Using Transceiver RX Pin as CDR Reference Clock
• Using Transceiver RX Pin as TX PLL Reference Clock

2.5 Interface Signals

The tables list the signals for the Intel FPGA HDMI IP core design example.
Table 15. Top-Level Signals
Signal
clk_fpga_b3_p
clk_50
user_pb
cpu_resetn
user_led_g
user_led_r
fmcb_gbtclk_m2c_p_0
fmcb_dp_m2c_p
fmcb_dp_c2m_p
fmcb_la_rx_p_9
fmcb_la_rx_p_8
fmcb_la_rx_n_8
®
Intel FPGA HDMI Design Example User Guide for Intel
26
2 Intel FPGA HDMI Design Example Detailed Description
Signal Name in Design
i2c_clk
Direction
On-board Oscillator Signal
Input
Input
User Push Buttons and LEDs
Input
Input
Output
Output
HDMI FMC Daughter Card Pins on FMC Port B
Input
Input
Output
Input
Inout
Inout
®
Arria 10 Devices
Description
• AVMM interfaces for reconfiguration
The frequency range requirement is between 100–125
MHz.
• PHY reset controller for transceiver reset sequence
The frequency range requirement is between 1–500
MHz.
• IOPLL Reconfiguration
Maximum clock frequency is 100 MHz.
• RX Reconfiguration for management
• CPU
2
• I C Master
A 50 MHz clock input that clocks I
in the HDMI RX core, and EDID RAM.
Width
1 100 MHz free running clock
1 50 MHz free running clock
1 Push button to control the Intel FPGA
HDMI design functionality
1 Global reset
8 Green LED display
8 Red LED display
1 HDMI RX TMDS clock
3 HDMI RX red, green, and blue data
channels
4 HDMI TX clock, red, green, and blue data
channels
1 HDMI RX +5V power detect
1 HDMI RX hot plug detect
2
1 HDMI RX I C SDA
UG-20077 | 2017.11.06
2
C slave, SCDC registers
Description
continued...