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2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Module
2
I
C Master
IOPLL
Transceiver PHY Reset Controller
Transceiver Native PHY
•
HDMI TX Core—The IP core receives video data from the top level and
performs TMDS encoding, auxiliary data encoding, audio data encoding, video
data encoding, and scrambling.
•
TX Oversampler—The TX Oversampler module transmits data by repeating
each bit of the input word a given number of times and constructs the output
words. The oversampling factor can be 3, 4, or 5 depending on the TMDS
clock frequency. The TX oversampler assumes that the input word is only
valid every 3, 4, or 5 clock cycles according to the oversampling factor. This
block is enabled when the outgoing data stream is below the minimum link
rate of the TX transceiver. When FPLL input reference clock frequency is
below 50 MHz, the allowable data rate must be below 1,500 Mbps.
(Refer to
Table 9
on page 18.)
•
DCFIFO —The DCFIFO transfers data from the TX link speed clock domain to
the transceiver parallel clock out domain. When the Nios II processor
determines the outgoing data stream is below the TX transceiver minimum
data rate, the TX transceiver accepts the data from the TX oversampler.
Otherwise, the TX transceiver reads the data directly from the DCFIFO with a
read request asserted at all times.
•
Clock Enable Generator—A logic that generates a clock enable pulse. This
clock enable pulse asserts every 5 clock cycles and serves as a read request
signal to clock the data out from the DCFIFO.
2
I
C is the interface used for Sink Display Data Channel (DDC) and Status and
Data Channel (SCDC). The HDMI source uses the DDC to determine the
capabilities and characteristics of the sink by reading the Enhanced Extended
Display Identification Data (E-EDID) data structure.
2
•
As DDC, I
C Master reads the EDID from the external sink to configure the
EDID information EDID RAM in the HDMI RX Top or for video processing.
2
•
As SCDC, I
C master transfers the SCDC data structure from the FPGA source
to the external sink for HDMI 2.0 operation. For example, if the outgoing data
stream is above 3,400 Mbps, the Nios II processor commands the I
to update the
TMDS_BIT_CLOCK_RATIO
the sink SCDC configuration register to 1.
The IOPLL supplies the link speed clock and video clock from the incoming TMDS
clock.
•
Output clock 1 (Link speed clock)
•
Output clock 2 (Video clock)
Note: The default IOPLL configuration is not valid for any HDMI resolution. The
IOPLL is reconfigured to the appropriate settings upon power up.
The Transceiver PHY reset controller ensures a reliable initialization of the TX
transceivers. The reset input of this controller is triggered from the top level, and
it generates the corresponding analog and digital reset signal to the Transceiver
Native PHY block according to the reset sequencing inside the block.
The
output signal from this block also functions as a reset signal to
tx_ready
the Intel FPGA HDMI IP core to indicate the transceiver is up and running, and
ready to receive data from the core.
Hard transceiver block that receives the parallel data from the HDMI TX core and
serializes the data from transmitting it.
Reconfiguration interface is enabled in the TX Native PHY block to demonstrate
the connection between TX Native PHY and transceiver arbiter. No
reconfiguration is performed for TX Native PHY.
Note: To meet the HDMI TX inter-channel skew requirement, set the TX channel
bonding mode option in the Intel Arria 10 Transceiver Native PHY
parameter editor to PMA and PCS bonding. You also need to add the
maximum skew (
set_max_skew
reset signal from the transceiver reset controller (
recommended in the Intel Arria 10 Transceiver PHY User Guide.
®
Intel
FPGA HDMI Design Example User Guide for Intel
Description
and
SCRAMBLER_ENABLE
) constraint requirement to the digital
tx_digitalreset
2
C master
bits of
) as
continued...
®
Arria 10 Devices
17
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