Intel Arria 10 series User Manual page 30

gxb_tx_cal_busy_out
gxb_tx_cal_busy_in
iopll_locked
txpll_locked
gxb_reconfig_write
gxb_reconfig_read
gxb_reconfig_address
gxb_reconfig_writedata
gxb_reconfig_readdata
gxb_reconfig_waitrequest
/
pll_reconfig_write
tx_pll_reconfig_write
/
pll_reconfig_read
tx_pll_reconfig_read
pll_reconfig_address
tx_pll_reconfig_address
pll_reconfig_writedata
tx_pll_reconfig_writedata
pll_reconfig_readdata
tx_pll_reconfig_readdata
pll_reconfig_waitrequest
tx_pll_reconfig_waitrequest
os
measure
ctrl
mode
TMDS_Bit_clock_Ratio
Scrambler_Enable
audio_de
audio_mute
®
Intel FPGA HDMI Design Example User Guide for Intel
30
TX Transceiver and IOPLL Signals
Output
Input
Output
Output
Input
Input
Input
Input
Output
Output
TX IOPLL and TX PLL Reconfiguration Signals
Input
Input
Input
/
Input
/
Output
/
Output
/
Input
Input
HDMI TX Core Signals
Input
Input
Input
Input
Input
Input
®
Arria 10 Devices
2 Intel FPGA HDMI Design Example Detailed Description
4 TX Native PHY calibration busy signal to
the transceiver arbiter
4 Calibration busy signal from the
transceiver arbiter to the TX Native PHY
1 Indicate IOPLL is locked
1 Indicate TX PLL is locked
4 Transceiver reconfiguration Avalon-MM
interface from the TX Native PHY to the
4 transceiver arbiter
40
128
128
4
1 TX IOPLL/TX PLL reconfiguration Avalon-
MM interfaces
1
10
32
32
1
2 Oversampling factor:
• 0: No oversampling
• 1: 3× oversampling
• 2: 4× oversampling
• 3: 5× oversampling
24 Indicates the TMDS clock frequency of the
transmitting video resolution.
6*N HDMI TX core control interfaces
Note: N = Symbols per clock
1
1 SCDC register interfaces
1
1 HDMI TX core audio interfaces
1
UG-20077 | 2017.11.06
continued...