Intel Arria 10 series User Manual page 24

Figure 10. Intel FPGA HDMI Design Example Clocking Scheme
Top
RX Top
Transceiver PHY
Reset Controller
Reconfiguration
RX Transceiver Clock Out
RX Link Speed Clock
RX Video Clock
RX CDR Reference Clock
Table 14. Clocking Scheme Signals
Clock
TX IOPLL/ TX PLL Reference
Clock
TX Transceiver Clock Out
TX PLL Serial Clock
TX/RX Link Speed Clock
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Intel FPGA HDMI Design Example User Guide for Intel
24
RX Core Top
PIO
RX Core
I C Slave
2
RX
(EDID)
Oversampler
I C Slave
2
DCFIFO
(EDID)
EDID RAM
IOPLL
RX Native PHY
IOPLL
RX Reconfiguration
Management
TX PLL Serial Clock
TX Transceiver Clock Out
TX Link Speed Clock
TX Video Clock
Signal Name in Design
hdmi_clk_in
tx_clk
tx_bonding_clocks
ls_clk
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Arria 10 Devices
2 Intel FPGA HDMI Design Example Detailed Description
TX Top
TX Core Top
CPU Sub-System
Oversampler
Clock Enable
Generator
RX-TX Link
Transceiver
TX Native PHY
Arbiter
Reconfiguration
Management Clock
I C Clock
2
RX TMDS Clock
TX IOPLL/TX PLL Reference Clock
Description
Reference clock to the TX IOPLL and TX PLL. The clock
frequency is the same as the expected TMDS clock
frequency from the HDMI TX TMDS clock channel.
For this Intel FPGA HDMI design example, this clock is
connected to the RX TMDS clock for demonstration purpose.
In your application, you need to supply a dedicated clock
with TMDS clock frequency from a programmable oscillator
for better jitter performance.
Note: Do not use a transceiver
reference clock. Your design will fail to fit if you
place the HDMI TX refclk on an
Clock out recovered from the transceiver, and the frequency
varies depending on the data rate and symbols per clock.
TX transceiver clock out frequency = Transceiver data rate/
(Symbol per clock*10)
Serial fast clock generated by TX PLL. The clock frequency is
set based on the data rate.
Link speed clock. The link speed clock frequency depends
on the expected TMDS clock frequency, oversampling factor,
symbols per clock, and TMDS bit clock ratio.
UG-20077 | 2017.11.06
PIO
TX Core
I C
2
TX
Master
DCFIFO
TX PLL IOPLL
Transceiver PHY
Reset Controller
IOPLL
pin as a TX PLL
RX
pin.
RX
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