Intel Arria 10 series User Manual page 15

Fpga hdmi design example

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2 Intel FPGA HDMI Design Example Detailed Description

UG-20077 | 2017.11.06

Module

PIO

To apply the

, include

Quartus INI

"permit_nf_pll_reconfig_out_of_lock=on"

place in the file the Intel Quartus Prime project directory. You should see a

warning message when you edit the IOPLL reconfiguration block

(pll_hdmi_reconfig) in the Quartus Prime software with the

Note: Without this

Quartus INI

the IOPLL loses lock during reconfiguration.

The parallel input/output (PIO) block functions as control, status and reset

interfaces to or from the CPU sub-system.

Intel

FPGA HDMI Design Example User Guide for Intel

Description

in the

quartus.ini

INI

, IOPLL reconfiguration cannot be completed if

file and

Arria 10 Devices

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