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2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
ctrl
locked
vid_lock
in_5v_power
hdmi_rx_hpd_n
hdmi_rx_i2c_sda
hdmi_rx_i2c_scl
edid_ram_access
edid_ram_address
edid_ram_write
edid_ram_read
edid_ram_readdata
edid_ram_writedata
edid_ram_waitrequest
Table 17.
HDMI TX Top-Level Signals
Signal
mgmt_clk
reset
hdmi_clk_in
vid_clk_out
ls_clk_out
sys_init
reset_xcvr
reset_pll
reset_pll_reconfig
tx_serial_data
gxb_tx_ready
HDMI RX Core Signals
Output
N*6
Output
3
Output
1
Input
1
Inout
1
2
I
C Signals
Inout
1
Inout
1
RX EDID RAM Signals
Input
1
Input
8
Input
1
Input
1
Output
8
Input
8
Output
1
Direction
Width
Clock and Reset Signals
Input
1
Input
1
Input
1
Output
1
Output
8
Output
1
Input
1
Input
1
Output
1
TX Transceiver and IOPLL Signals
Output
4
Output
1
®
Intel
FPGA HDMI Design Example User Guide for Intel
Note: N = symbols per clock
HDMI RX 5V detect and hotplug detect
HDMI RX DDC and SCDC interface
HDMI RX EDID RAM access interface.
Assert
when you want
edid_ram_access
to write or read from the EDID RAM, else
this signal should be kept low.
Description
System clock input (100 MHz)
System reset input
Reference clock to TX IOPLL and TX PLL.
The clock frequency is the same as the
TMDS clock frequency.
Video clock output
Link speed clock output
System initialization to reset the system
upon power-up
Reset to TX transceiver
Reset to IOPLL and TX PLL
Reset to PLL reconfiguration
HDMI serial data from the TX Native PHY
Indicates TX Native PHY is ready
continued...
®
Arria 10 Devices
29
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