Table of Contents
Advertisement
Signal
rx_aux_data
hdmi_tx_de
hdmi_tx_hsync
hdmi_tx_vsync
hdmi_tx_data
tx_audio_format
tx_audio_metadata
tx_audio_info_ai
tx_audio_CTS
tx_audio_N
tx_audio_de
tx_audio_data
tx_gcp
tx_info_avi
tx_info_vsi
tx_aux_eop
tx_aux_sop
tx_aux_valid
tx_aux_data
tx_aux_ready
Table 20.
Qsys System Signals
cpu_clk
cpu_clk_reset_n
tmds_bit_clock_ratio_pio_external_connectio
n_export
measure_pio_external_connection_export
measure_valid_pio_external_connection_expor
t
oc_i2c_master_av_slave_translator_avalon_an
ti_slave_0_address
oc_i2c_master_av_slave_translator_avalon_an
ti_slave_0_write
oc_i2c_master_av_slave_translator_avalon_an
ti_slave_0_readdata
®
Intel
FPGA HDMI Design Example User Guide for Intel
34
Direction
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Signal
®
Arria 10 Devices
2 Intel FPGA HDMI Design Example Detailed Description
Width
72
N
HDMI TX video interfaces
Note: N = symbols per clock
N
N
N*48
5
HDMI TX audio interfaces
165
48
20
20
1
256
6
HDMI TX sideband interfaces
112
61
1
HDMI TX auxiliary interfaces
1
1
72
1
Direction
Width
Input
1
Input
1
Input
1
Input
24
Input
1
Output
3
Output
1
32
UG-20077 | 2017.11.06
Description
Description
CPU clock
CPU reset
TMDS bit clock ratio
Expected TMDS clock
frequency
Indicates measure PIO is
valid
2
I
C Master Avalon-MM
interfaces
continued...
Advertisement
Table of Contents
