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reconfig_mgmt_write
reconfig_mgmt_read
reconfig_mgmt_address
reconfig_mgmt_writedata
reconfig_mgmt_readdata
reconfig_mgmt_waitrequest
TMDS_Bit_clock_Ratio
audio_de
audio_data
audio_info_ai
audio_N
audio_CTS
audio_metadata
audio_format
aux_pkt_data
aux_pkt_addr
aux_pkt_wr
aux_data
aux_sop
aux_eop
aux_valid
aux_error
gcp
info_avi
info_vsi
colordepth_mgmt_sync
vid_data
vid_vsync
vid_hsync
vid_de
mode
®
Intel
FPGA HDMI Design Example User Guide for Intel
28
2 Intel FPGA HDMI Design Example Detailed Description
RX Reconfiguration Management
Output
1
Output
1
Output
12
Output
32
Input
32
Input
1
HDMI RX Core Signals
Output
1
Output
1
Output
256
Output
48
Output
20
Output
20
Output
165
Output
5
Output
72
Output
6
Output
1
Output
72
Output
1
Output
1
Output
1
Output
1
Output
6
Output
112
Output
61
Output
2
Output
N*48
Output
N
Output
N
Output
N
Output
1
®
Arria 10 Devices
UG-20077 | 2017.11.06
•
0: No oversampling
•
1: 5× oversampling
RX reconfiguration management Avalon-
MM interface to transceiver arbiter
SCDC register interfaces
HDMI RX core audio interfaces
HDMI RX core auxiliary interfaces
HDMI RX core sideband signals
HDMI RX core video ports
Note: N = symbols per clock
HDMI RX core control and status ports
continued...
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