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Module
2
I
C Slave
EDID RAM
IOPLL
Transceiver PHY Reset Controller
RX Native PHY
RX Reconfiguration Management
IOPLL Reconfiguration
®
Intel
FPGA HDMI Design Example User Guide for Intel
14
2 Intel FPGA HDMI Design Example Detailed Description
•
HDMI RX Core—The IP core receives the serial data from the Transceiver
Native PHY and performs data alignment, channel deskew, TMDS decoding,
auxiliary data decoding, video data decoding, audio data decoding, and
descrambling.
•
RX Oversampler—The RX Oversampler module extracts data from the
oversampled incoming data stream when the detected clock frequency band
is below the transceiver minimum link rate. The oversampling factor is fixed
at 5 and you can program the data width to support different number of
symbols. For Intel Arria 10 devices, the supported data width is 20 bits for 2
symbols per clock. The extracted bit is accompanied by a data valid pulse
asserted every 5 clock cycles.
•
DCFIFO —The DCFIFO transfers data from the RX transceiver recovered clock
domain to the RX link speed clock domain.
2
I
C is the interface used for Sink Display Data Channel (DDC) and Status and
Data Channel (SCDC). The HDMI source uses the DDC to determine the
capabilities and characteristics of the sink by reading the Enhanced Extended
Display Identification Data (E-EDID) data structure.
2
•
The 8-bit I
C slave addresses for E-EDID are 0xA0 and 0xA1. The LSB
indicates the access type: 1 for read and 0 for write. When an HPD event
2
occurs, the I
C slave responds to E-EDID data by reading from the RAM.
2
•
The I
C slave-only controller also supports SCDC for HDMI 2.0 operations.
2
The 9-bit I
C slave address for the SCDC are 0xA8 and 0xA9. When an HPD
2
event occurs, the I
C slave performs write or read transaction to or from
SCDC interface of the HDMI RX core.
2
Note: This I
C slave-only controller for SCDC is not required if HDMI 2.0 is
not intended.
The design stores the EDID information using the RAM 1-port IP core. A standard
two-wire (clock and data) serial bus protocol (I
the CEA-861-D Compliant E-EDID data structure. This EDID RAM stores the E-
EDID information.
The IOPLL generates the RX CDR reference clock, link speed clock, and video
clock for the incoming TMDS clock.
•
Output clock 0 (CDR reference clock)
•
Output clock 1 (Link speed clock)
•
Output clock 2 (Video clock)
Note: The default IOPLL configuration is not valid for any HDMI resolution. The
IOPLL is reconfigured to the appropriate settings upon power up.
The Transceiver PHY reset controller ensures a reliable initialization of the RX
transceivers. The reset input of this controller is triggered by the RX
reconfiguration, and it generates the corresponding analog and digital reset
signal to the Transceiver Native PHY block according to the reset sequencing
inside the block.
Hard transceiver block that receives the serial data from an external video
source. It deserializes the serial data to parallel data before passing the data to
the HDMI RX core.
RX reconfiguration management that implements rate detection circuitry with the
HDMI PLL to drive the RX transceiver to operate at any arbitrary link rates
ranging from 250 Mbps to 6,000 Mbps.
Refer to the Multi-Rate Reconfiguration Sequence Flow figure below.
IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs
in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth
in real-time, without reconfiguring the entire FPGA. This blocks runs at 100 MHz
in Intel Arria 10 devices.
Due to IOPLL reconfiguration limitation, apply the
permit_nf_pll_reconfig_out_of_lock=on
reconfiguration IP generation.
®
Arria 10 Devices
UG-20077 | 2017.11.06
Description
2
C slave-only controller) transfers
Quartus INI
during the IOPLL
continued...
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