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Table 18.
Transceiver Arbiter Signals
Signal
clk
reset
rx_rcfg_en
tx_rcfg_en
rx_rcfg_ch
tx_rcfg_ch
rx_reconfig_mgmt_write
rx_reconfig_mgmt_read
rx_reconfig_mgmt_address
rx_reconfig_mgmt_writedata
rx_reconfig_mgmt_readdata
rx_reconfig_mgmt_waitrequest
tx_reconfig_mgmt_write
tx_reconfig_mgmt_read
tx_reconfig_mgmt_address
tx_reconfig_mgmt_writedata
tx_reconfig_mgmt_readdata
tx_reconfig_mgmt_waitrequest
reconfig_write
reconfig_read
reconfig_address
reconfig_writedata
rx_reconfig_readdata
rx_reconfig_waitrequest
tx_reconfig_readdata
tx_reconfig_waitrequest
rx_cal_busy
®
Intel
FPGA HDMI Design Example User Guide for Intel
32
2 Intel FPGA HDMI Design Example Detailed Description
Direction
Width
Input
1
Input
1
Input
1
Input
1
Input
2
Input
2
Input
1
Input
1
Input
10
Input
32
Output
32
Output
1
Input
1
Input
1
Input
10
Input
32
Output
32
Output
1
Output
1
Output
1
Output
10
Output
32
Input
32
Input
1
Input
1
Input
1
Input
1
®
Arria 10 Devices
UG-20077 | 2017.11.06
Description
Reconfiguration clock. This clock must
share the same clock with the
reconfiguration management blocks.
Reset signal. This reset must share the
same reset with the reconfiguration
management blocks.
RX reconfiguration enable signal
TX reconfiguration enable signal
Indicates which channel to be
reconfigured on the RX core. This signal
must always remain asserted.
Indicates which channel to be
reconfigured on the TX core. This signal
must always remain asserted.
Reconfiguration Avalon-MM interfaces
from the RX reconfiguration management
Reconfiguration Avalon-MM interfaces
from the TX reconfiguration management
Reconfiguration Avalon-MM interfaces to
the transceiver
Calibration status signal from the RX
transceiver
continued...
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