Intel Arria 10 series User Manual page 18

Module
TX PLL
IOPLL Reconfiguration
PIO
Table 9. Transceiver Data Rate and Oversampling Factor for Each TMDS Clock
Frequency Range
TMDS Clock Frequency
(MHz)
85–150
100–340
50–100
35–50
30–35
25–30
Table 10. Top-Level Common Blocks
Module
Transceiver Arbiter
®
Intel FPGA HDMI Design Example User Guide for Intel
18
The transmitter PLL block provides the serial fast clock to the Transceiver Native
PHY block. For this Intel FPGA HDMI design example, fPLL is used as TX PLL.
IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs
in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth
in real-time, without reconfiguring the entire FPGA. This blocks runs at 100 MHz
in Intel Arria 10 devices.
Due to IOPLL reconfiguration limitation, apply the
permit_nf_pll_reconfig_out_of_lock=on
reconfiguration IP generation.
To apply the
Quartus INI
"permit_nf_pll_reconfig_out_of_lock=on"
place in the file the Intel Quartus Prime project directory. You should see a
warning message when you edit the IOPLL reconfiguration block
(pll_hdmi_reconfig) in the Quartus Prime software with the
Note: Without this
the IOPLL loses lock during reconfiguration.
The parallel input/output (PIO) block functions as control, status and reset
interfaces to or from the CPU sub-system.
TMDS Bit clock Ratio Oversampling Factor
1
0
0
0
0
0
This generic functional block prevents transceivers from recalibrating
simultaneously when either RX or TX transceivers within the same physical
channel require reconfiguration. The simultaneous recalibration impacts
applications where RX and TX transceivers within the same channel are assigned
to independent IP implementations.
This transceiver arbiter is an extension to the resolution recommended for
merging simplex TX and simplex RX into the same physical channel. This
transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and
TX reconfiguration requests targeting simplex RX and TX transceivers within a
channel as the reconfiguration interface port of the transceivers can only be
accessed sequentially.
The interface connection between the transceiver arbiter and TX/RX Native
PHY/PHY Reset Controller blocks in this design example demonstrates a generic
mode that apply for any IP combination using the transceiver arbiter. The
transceiver arbiter is not required when only either RX or TX transceiver is used
in a channel.
The transceiver arbiter identifies the requester of a reconfiguration through its
Avalon-MM reconfiguration interfaces and ensures that the corresponding
tx_reconfig_cal_busy
®
Arria 10 Devices
2 Intel FPGA HDMI Design Example Detailed Description
Description
, include
, IOPLL reconfiguration cannot be completed if
Quartus INI
Transceiver Data Rate (Mbps)
Not applicable
Not applicable
5
3
4
5
Description
or
rx_reconfig_cal_busy
UG-20077 | 2017.11.06
Quartus INI
during the IOPLL
in the file and
quartus.ini
.
INI
3400–6000
1000–3400
2500–5000
1050–1500
1200–1400
1250–1500
is gated accordingly.
continued...