Intel Arria 10 series User Manual page 16

Figure 7. Multi-Rate Reconfiguration Sequence Flow
The figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receivers input data
stream and reference clock frequency, or when the transceiver is unlocked.
Table 8. HDMI TX Top Components
Module
TX Core Top
®
Intel FPGA HDMI Design Example User Guide for Intel
16
Reset the RX HDMI PLL and RX transceiver.
Enable the rate detection circuit to measure incoming TMDS clock.
Accept acknowledgement with clock frequency band and desired
RX HDMI PLL and RX transceiver settings.
Determine if RX HDMI PLL and/or RX transceiver reconfiguration
is required based on the previous and current detected clock
frequency band and color depth. Different color depths may fall
within the same clock frequency band.
Reconfiguration Required
Request RX HDMI PLL and/or RX transceiver reconfiguration if the
previous and current clock frequency band or color depth differs.
The controller reconfigures the RX HDMI PLL and/or RX transceiver
(followed by recalibration on Intel Arria 10 device).
When all reconfiguration processes complete or the previous and
current clock frequency band and color depth do not differ, reset
the RX HDMI PLL and RX transceiver.
Enable rate the detection circuit periodically to monitor the
reference clock frequency. If the clock frequency band changes or
the RX HDMI PLL or RX transceiver or HDMI core lose lock, repeat
the process.
The TX Core top level consists of:
®
Arria 10 Devices
2 Intel FPGA HDMI Design Example Detailed Description
Description
UG-20077 | 2017.11.06
Reconfiguration
Not Required
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