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2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Module
RX-TX Link
CPU Sub-System
For HDMI application, only RX initiates reconfiguration. By channeling the
Avalon-MM reconfiguration request through the arbiter, the arbiter identifies that
the reconfiguration request originates from the RX, which then gates
from asserting and allows
tx_reconfig_cal_busy
to assert. The gating prevents the TX transceiver from being moved to
calibration mode unintentionally.
Note: Because HDMI only requires RX reconfiguration, the
tx_reconfig_mgmt_*
is not required between the arbiter and the TX Native PHY block. The
blocks are assigned to the interface in the design example to demonstrate
generic transceiver arbiter connection to TX/RX Native PHY/PHY Reset
Controller.
•
The video data output and synchronization signals from HDMI RX core loop
through a DCFIFO across the RX and TX video clock domains.
•
The General Control Packet (GCP), InfoFrames (AVI, VSI and AI), auxiliary
data, and audio data loop through DCFIFOs across the RX and TX link speed
clock domains.
•
The auxiliary data port of the HDMI TX core controls the auxiliary data that
flow through the DCFIFO through backpressure. The backpressure ensures
there is no incomplete auxiliary packet on the auxiliary data port.
•
This block also performs external filtering:
— Filters the audio data and audio clock regeneration packet from the
auxiliary data stream before transmitting to the HDMI TX core auxiliary
data port.
Note: To disable this filtering, press
ensure there is no duplication of audio data and audio clock
regeneration packet in the retransmitted auxiliary data stream.
— Filters the High Dynamic Range (HDR) Infoframe from the HDMI RX
auxiliary data and inserts an example HDR Infoframe to the auxiliary data
of the HDMI TX through the Avalon ST multiplexer.
The CPU sub-system functions as SCDC and DDC controllers, and source
reconfiguration controller.
•
The source SCDC controller contains the I
master controller transfers the SCDC data structure from the FPGA source to
the external sink for HDMI 2.0 operation. For example, if the outgoing data
stream is 6,000 Mbps, the Nios II processor commands the I
controller to update the
TMDS_BIT_CLOCK_RATIO
bits of the sink TMDS configuration register to 1.
2
•
The same I
C master also transfers the DDC data structure (E-EDID) between
the HDMI source and external sink.
•
The Nios II CPU acts as the reconfiguration controller for the HDMI source.
The CPU relies on the periodic rate detection from the RX Reconfiguration
Management module to determine if the TX requires reconfiguration. The
Avalon-MM slave translator provides the interface between the Nios II
processor Avalon-MM master interface and the Avalon-MM slave interfaces of
the externally instantiated HDMI source's IOPLL and TX Native PHY.
•
The reconfiguration sequence flow for TX is same as RX, except that the PLL
and transceiver reconfiguration and the reset sequence is performed
sequentially. Refer to
Figure 8
®
Intel
FPGA HDMI Design Example User Guide for Intel
Description
rx_reconfig_cal_busy
signals are tied off. Also, the Avalon-MM interface
. Enable this filtering to
user_pb[2]
2
C master controller. The I
and
SCRAMBLER_ENABLE
on page 20.
2
C
2
C master
®
Arria 10 Devices
19
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