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2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Figure 9.
RX-TX Link with Dynamic Range and Mastering InfoFrame Insertion
The figure shows the block diagram of RX-TX link including Dynamic Range and Mastering InfoFrame insertion
into the HDMI TX core auxiliary stream.
HDMI RX
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Table 11.
Auxiliary Data Insertion Block (altera_hdmi_aux_hdr) Signals
Signal
clk_clk
reset_reset_n
multiplexer_out_data
multiplexer_out_valid
multiplexer_out_ready
multiplexer_out_startofpacket
multiplexer_out_endofpacket
multiplexer_out_channel
multiplexer_in_data
multiplexer_in_valid
multiplexer_in_ready
multiplexer_in_startofpacket
multiplexer_in_endofpacket
RX-TX Link
RX Video
Video
Bypass FIFO
RX Audio
Audio
Bypass FIFO
RX Sideband
Sideband
Bypass FIFO
block_ext_hdr_infoframe
RX Auxiliary
Auxiliary
Auxiliary
Bypass FIFO
Packet Filter
Clock and Reset
Auxiliary Packet Generator and Multiplexer Signals
®
Intel
Auxiliary Data Insertion Block
Auxiliary Data Interface
Auxiliary InfoFrame
HDR
Content Interface
Data
Auxiliary
Packet
Auxiliary Insertion
Generator
AUX
Control Interface
Insertion
Control
Direction
Width
Input
1
Input
1
Output
72
Output
1
Output
1
Output
1
Output
1
Output
11
Input
72
Input
1
Input
1
Input
1
Input
1
FPGA HDMI Design Example User Guide for Intel
TX Video
TX Audio
TX Sideband
HDMI TX
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In1
TX Auxiliary
Multiplexer
In0
Description
Clock input. This clock should be
connected to the link speed
clock.
Reset input.
Avalon streaming output from
the multiplexer.
Avalon streaming input to the
port of the multiplexer.
In1
®
Arria 10 Devices
21
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