Communication Options; Output Ports; Ieee-488 (Option 001) - Wavetek 75 Instruction Manual

The amplitude and offset control circuits (ref: schematic
01 03-00-1 456 sheet 4) must be driven with
+
5V logic
levels. To accomplish this, three of the shift registers
(Ul3, U18 and U19) are run on
&
5Vpower supplies. The
multiplexer, U11, acts as a level shifter to change the
normal 0 to 5V logic into 2 5V logic in order to properly
drive U13, U18and U19. U11 isactually threesingle pole
double throw analog switches. One contact of each
switch is connected to
+
W a n d the other contact is con-
nected to
-
5V. The wipersof each switch appear at pins
14,15 and 4. The data line(SERD), clock line (SERC) and
the enable (ANLE) are connected to the control pins for
the switches (pins 9, 10 and 11). When the control pin
is low, the wiper of the switch is connected to the
-
5V
contact causing a logic low output. When the control pin
is high, the wiper is connected to the
+
5V contact
causing a logic high output.
4.2.3.9 Output Ports
Refer to schematic 01 03-00-1 389, sheets 2 and 4. The
output ports provide a parallel interface from the
microprocessor to the dedicated circuits. The output
ports can be divided into two blocks, the burst counter
preload and the start address preload. The output ports
are driven by the latched data bus (LDB7-LDBO). The
latched data bus is created by the octal transparent latch
(U46). The microprocessor's data bus is connected to
the inputsof U46(pins 3,4,7,8,13,14,17 and 18). The "E"
clock is connected to the clock input of U46 (pin 11).
When the data on the data bus (AD7-ADO) is valid, the
"Em clock goes low and the data is latched into the out-
puts of U46. The purposeof this latch is to reduce loading
on the microprocessor data bus and to improve the hold
time of the data for the output ports.
The burst counter preload (ref: schematic 01 03-00-1 389
sheet 4) provides a 20 bit binary number for the burst
counter. It consists of three octal D type flip flops (U49,
U45 and U39). The start address preload (ref: schematic
01 03-00-1 389 sheet 2) provides the 13 bit waveform start
address to the waveform address counter. It is com-
prised of two of the same type of octal flip flops(U26 and
U22). In both circuit blocks, the information present on
the D inputsof the latches(pins3,4,7,8,13,14,17and 18)
is transferred to the Q outputs (pins 2,5,6,9,12,15,16and
19) on the rising edge of the clock input (pin 11). When
the microprocessor writes to one of the output ports, it
places the data on its data bus (AD7-ADO) where it is
latched by U46. The address decoder selects which out-
put port is being addressed and pulls the appropriate
Besides the control busses mentioned above, the out-
put ports also supply 6 individual control lines. On U26,
are three lines ( = D , PCLK, and S ~ R ) that are
used during a return to start. On U39, are three lines
(SLOPE, MANHOLD andTRIGGERMASK) that are used
in the trigger and hold logic.
4.2.4 Communication Options
4.2.4.1 General Description
The communication options provide a means for the user
to enter and query instrument parameters and waveform
informationvia an external computer or instrument con-
troller. Either an IEEE-488 parallel interface(option 001)
or a RS-232-C serial interface (option 002) may be
installed.
4.2.4.2 IEEE-488 (Option 001)
Refer to schematic 01 03-00-1 678. The IEEE-488 option,
also referred to asGPIB(genera1 purpose interface bus)
consists of a general purpose interface adapter (U2), two
bus transceivers (U3 and U4), one hex buffer ( U l ) and
one 5 position SPSTswitch (SW1). All GPIB data transfers
and bus protocols are handled by the general purpose
interface adapter (GPIA). This device transfers data to
and from the bus via U3. The control lines are interfaced
to the bus through U4. These transceivers handle the
driving capability and line termination req,~:ements for
the GPIB bus and are enabled when the GPlA sets their
pin
1
high. For an explanation of the data and control lines
refer to Section 3.27.
The GPlA (U2) contains a data in register, a data out
register and several control registers. Information is
transferred between these registers and the micro-
processor via the microprocessor data bus (U2 pins
14-7). The microprocessor section enables the GPlA by
pulling COMM low (U2 pin 3). The data transfer is syn-
chronized by the "En clock on U2 pin 6. This is a 1 MHz
clock that originates in the microprocessor section.
RW
on U2 pin 5 is the readlwrite control from themicro-
processor. The microprocessor selects which register
is accessed with the three least significant address lines
(U2 pins 37,38 and 39). When the GPlA needs the atten-
tion of the microprocessor, it p u l l s m ( p i n 40) low.This
causes the microprocessor to execute an interrupt
service routine which interrogates the GPlA and trans-
fers the necessary information. Pin 19 of the GPlA is con-
nected to the master reset line
(m).
When the instru-
ment power is turned on, this line goes low and forces
the GPlA into a reset condition.
enable (U27 pins 15-1 1) low. When the enable is
When the instrument power is turned on, the micro-
released, the data is latched into the output port and is
processor executes an initialization routine for theGPIA.
available for the dedicated circuit.
As part of this routine, an address switch register is
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