Main Memory; Battery And Test Circuit; Front Panel And Front Panel Interface - Wavetek 75 Instruction Manual

The most significant address line (ADR15), using the
'inverter' U2A, selects the 32K byte block containing the
ROM. The combination of ADRl5 and ADRl4 are used
by U2A and the 'nand' gate U3A to generate ARBMEM
(U3Apin 3). This line is used to select the 16K byte block
containing the waveform memory. The decoder, U13
uses the four most significant address lines to select
either the main RAM, the communication option or one
of the 110 ports of the microprocessor. When one of the
110 ports is selected, llO(U13pin 15) is low.This enables
U9, which in conjunction with U27 further decodes the
address into smaller blocks and selects individual lines
or 110devices. The "E" clock is used as oneof the enable
lines for U27 to synchronize data transfer between the
microprocessor and the 110 devices.
4.2.3.5 Main Memory
Refer to schematic 01 03-00-1 389, sheet 2. The main
memory section contains a read only memory (ROM) and
a random access memory (RAM). The ROM (U3l) con-
tains 32,768 locations, each 8 bits wide and is the storage
location for the instrument software. The software con-
tains the instructions that drive the microprocessor. The
RAM (U21) contains 8,192 locations, each 8 bits wide
and is used to retain stored settings, and as a scratch
pad and temporary data storage for the microprocessor.
When the microprocessor accesses the main memory,
a read or write pulse must be generated to inform the
the RAM and ROM of the type of cycle being executed.
The "E" clock (U30 pin 40) and
RNV
(U30 pin 38) are
gated together by the "nand" gate, U3B to produce the
read pulse
(m).
This line pulses low when the micro-
processor is ready to accept data during a read cycle.
The write pulse is generated by gating
RIW
and EB
together at the "nand" gate U4B.Theoutput of U4B(pin
6) goes low when the microprocessor is ready to output
data during a write cycle.
When the ROM is accessed, the microprocessor outputs
the 1 6 bit address (ADR1 5-ADRO) of the desired loca-
tion. The lower 15 address lines (ADR14-ADRO) are used
by the ROM to determine the location to be output. The
address decoder section determines the memory block
being accessed and pulls the chip enable (U31 pin 20)
low. The ROM then puts the data stored in that location
on the data bus (AD7-ADO) for the microprocessor to
read.
The microprocessor can either read from or write to the
RAM. To write data into the RAM, the write enable (pin
27) must be pulled low. To read data from the RAM the
output enable (pin 20) must be pulled low. When the
microprocessor accesses the RAM, the address of the
desired location is put onto the address bus
(ADR15-ADRO). The address decoder section pulls the
chip select (RAM) on pin 200f the RAM low. ADR12-ADRO
are used by the RAM to determine the location to be
accessed. Depending on the type of cycle being
executed, either the output enable (pin 22) or the write
enable (pin 27) is pulled low and the data transfer takes
place.
The RAM receives its power from the battery backed up
supply (BBV). This allows the memory to retain the
instrument setup when the power is turned off. While the
instrument power is off, the RAM is still powered and its
output enable (pin 22) is low. Unless it is disabled it will
try to drive the data bus, consuming more power and
drainiqg the battery. The resistor, R17, and the analog
switch, U1 A, facilitate this by pulling the chip select line
high when the power is off. During normal operation the
reset line(m) is high and the switches in U1 Aareclosed.
When the instrument power is turned off, is pulled
low by the power onloff reset circuit (ref: schematic
01 03-00-1 389sheet 2)which opens theswitches in U1A.
The chip select for the RAM (U21 pin 20) is then pulled
high through R17 and the memory is disabled.
4.2.3.6 Battery and Test Circuit
Refer to schematic 01 03-00-1 389, sheet 2. The main
component of this circuit is a BR213A lithium battery
(BT1). U20B is a voltage comparator used to test the
battery voltage and interface to the microprocessor.
While the instrument power is turned on, the battery
backed up supply (BBV) receives its power from the
+
5V
supply. Once the
+
5V supply drops below the battery
voltage, nominally
+
3V, the power supplied to BBV is
sourced by the battery. The diode, CR2, prevents the
battery from discharging into the
+
5V supply when the
instrument power is turned off. CR3 prevents the
+
5V
supply from charging the battery while the instrument
is turned on.
When the microprocessor tests the battery it pulls
BLOAD low which places a slight load on it through the
resistor R18. The battery voltage is then compared
against the minimum threshold voltage set by R20 and
R21. If the battery is good and its voltage is higher than
the threshold, U20B pulls BTST (U20B pin 1) low. If the
battery voltage is lower than the threshold, the resistor
R23 pulls BTST high. This line is read by the
microprocessor to determine the status of the battery.
The microprocessor checks the battery when the instru-
ment power is first turned on and at regular intervalsdur-
ing normal operation.
4.2.3.7 Front Panel and Front Panel Interface
Refer to schematic 01 03-00-1 389, sheets 1 and 3, and
schematic 01 03-00-1 775. The front panel is the main
interface between the user and the instrument.
Scans by AI