Timing And Triggering; Frequency Synthesizer; Pll Switching And Vco Frequency - Wavetek 75 Instruction Manual

When ZBlT is high Q1 is turned on, pulling its collector
voltage low. This turns off 0 5 so the output is pulled low
through R28. When ZBlT is high Q1 is turned off so the
collector voltage is set by Q6. The output tracks this
voltage minus the Vbe drop of Q5. R29 and R30 provide
the 600 ohm output impedance of the circuit. Q2,Q3 and
0 4 are controlled by the lines ZL0,ZLl and ZL2. The lines
originate in the microprocessor and are interfaced to this
circuit by the control shift register (ref:schematic
01 03-00-1 456 sheet 2).
4.2.2 Timing And Triggering
4.2.2.1 General Description
The waveform clock controls the waveform address
counter and thus the sample frequency of the waveform.
The frequency of the waveform clock is generated either
in the frequency synthesizer, set by the user as sample
frequency or by an external reference. The trigger and
hold logic contains the circuitry to select which reference
is used and control the clock in the triggerable modes.
The burst counter works in conjunction with the trigger
and hold logic to control burst mode and acts as the
internal waveform counter.
4.2.2.2 Frequency Synthesizer
Refer to schematic 0103-00-1456, sheet 2. The fre-
quency synthesizer consists of two main circuit blocks,
the phase lock loop (PLL) and the frequency range
dividers. The main components of the PLL are a crystal
reference (Yl), phase detectorldivide by "N" (U36), dual
opamp(U30), avoltage controlled oscillator (U31), adual
JK flip flop (U32) and a eight input data selector (U37).
In general terms, the phase detector (U36) compares
the VCO (U3l) frequency with the crystal reference fre-
quency and sends a correction voltage to the VCO. This
maintains the VCO frequency at the same accuracy as
the crystal frequency. Before this comparison takes
place, the crystal is divided by 6,144 to 1 Khz. The VCO
frequency is alsodivided down to 1 Khz by a number "N"
which is programmable. Changing "N" causes the VCO
frequency to change to maintain the 1 Khz to the phase
detector and therefore the output frequency of the PLL
changes. Both thedivide by 6,144and the divide by "N"
are internal to U36. The divide by "N" is programmed
by the microprocessor through the lines SERC, SERD
and PLLE (U36 pins 1 0,11 and 1 2). The microprocessor
serially shifts in 16 bits of data on SERD, using SERC to
clock it in. When all 16 bits have been shifted in, PLLE
is pulled high to enable the new data. Of the 16 bits, 14
program the divide by "N" and 2are present on U36 pins
13 and 14 (SW1 and SW2). These 2 bits control the data
selector U37 which selects either the VCO frequency,
VC012 frequency or VC014 frequency to be applied to
the divide by "N" on U36 pin 9.
The phase detector in U36 compares the phase of the
1 Khz reference to the phase of the 1 Khz from the VCO
and outputs correction pulses on pin 6 (PD). This pulse
can be either positive or negative depending upon the
direction of the phase difference. U30A, R8 and C8 act
as an integrator to convert the pulses to a DC control
voltage. U30B, R9 and C9 provide a low pass filter to
stabilize the loop. The control voltage is then applied to
the frequency control input of theVCO(U31 pin 13).The
combination of the voltage on pin 2 and the capacitor
C l 1 determine the frequency range of the VCO. U32A
and U32B are flip flops configured as divide by 2's. These
provide the VC012 frequency and the VC014 frequency.
U37 selects one of the 3 different frequencies applied
to the DO-D3 inputs based on the two bit binary number
on it's A and B control inputs (pins 11 and 10). The
selected frequency appears on the output at pin 6. The
PLL divider switching and VCO frequency is shown in
table 4-1.
The frequency range divider consists of four dual
bi-quinary counters (U28, U33, U34 and U35) and one
8 bit data selector (U29). The counters (U35, U34, U33
and U28A) are configured as seven discrete divide by
10's. The output of the PLL is applied to the string of
dividers to produce eight different decades of frequency
range. The microprocessor controls the data selector
(U29)with three lines; FRBIT1 (U29pin 9), FRBIT2(U29
pin 10) and FRBIT3(U29 pin 11). The data selector uses
the binary number from these three lines to determine
which frequency range appears at its output on pin 5.
U28Bdivides this frequency by 5 and the final frequency
synthesizer output appears on pin 9 (INTREF). A truth
table for the frequency range control is shown in table
4-2.
Table 4-1. PLL Switching and VCO Frequency
Display Counts
1
i F i 3
VCO
Frequency
U31-8
9.999 MHz
-
8.000 MHz
7.999 MHz
-
4.000 MHz
7.998 MHz
-
4.000 MHz
7.996 MHz
-
4.000 MHz
2.000 MHz
1
1
1
1
10.000 MHz
Scans by ArtekMedia O 2006