Circuit Description; Signal Path; Waveform Address Counter; 1 Introduction - Wavetek 75 Instruction Manual

SECTION
4
CIRCUIT DESCRIPTION
4.1 INTRODUCTION
The purpose of this section is to familiarize the user or
service personnel with the circuit level operation of the
Model 75. This knowledge is necessary to aid in
troubleshooting of an instrument failure and may also
allow the user to gain greater insight into the Model 75's
versatility for particular applications.
The blockdiagram of the Model 75 is shown in figure 4-1.
This block diagram is grouped into 5 functional blocks:
Signal Path consisting of the waveform address
counter, waveform address selector, waveform
memory, waveform latch, waveform synthesizer,
amplitude and offset controls, output amplifier, out-
put attenuator, and Z-Axis driver.
Timing andTriggering consisting of the frequency
synthesizer, trigger and hold logic, and the burst
counter.
Instrument Control consisting of the micro-
processor and memory section, and the front
panel.
Communication Option, if any installed, consisting
of either an IEEE-488 card or an RS-232-C card.
Power Supply.
Refer to figure 6-1, Troubleshooting Block Diagram, for
a more detailed look at circuit block interaction.
4.2 DETAILED CIRCUIT DESCRIPTION
4.2.1 Signal Path
4.2.1.1 General Description
The waveform memory contains the digital waveform
data that originates from the microprocessor. The infor-
mation to be accessed is determined by the waveform
address counter which is updated at a rate determined
by the Timing and Triggering section. The digital
waveform information issent through thewaveform latch
to the waveform synthesizer which converts it to an
analog waveform. Any external signal applied to the Sum
In input is summed together with the internal waveform
at this point. The waveform is then run through the
amplitude control. This circuit controls the amplitude
within a 10 to 1 range based on data provided by the
microprocessor. The offset control converts the digital
information from the microprocessor to an analog
voltage and applies that voltage to the output amplifier.
The output amplifier sums the waveform and offset
voltages and provides the final waveform amplification.
The output attenuator controls the waveform amplitude
in 3 single decade steps and maintains the 50 ohm out-
put impedance.
4.2.1.2 Waveform Address Counter
Refer to schematic 01 03-00-1 389, sheet 3. The
waveform address counter consists of four cascaded
4 bit binarycounters(U24, U25, U28and U36).The binary
output of these counters provides the address, to the
waveform memory, of the digital waveform information
to be accessed. U24 pin 14 is the least significant
address bit and U36 pin 14 is the most significant. The
waveform start address, as set by the user, is applied
by the microprocessor to the preload inputs of the
counters (STRT12-STRTO). This address will appear on
the outputs of the counters when pin 9(LOAD) is pulled
low by the logic of U4C, U1OC and U35C. When pin 9
(m)
of the counters is released, the data on the
counter outputs will increment by one with every rising
edge on pin 2(CLK). TheCLK line originates in theTiming
andTriggering section and its frequency isset by the user
as sample frequency. When U24 counts from the binary
number set by its preload inputs to binary 1 1 1 1, U24 pin
15 (Ripple Carry Out) goes high and enables U25 for 1
count. This sequence repeats until U25 has counted to
binary 1 11 1, when its ripple carry out will go highenabling
U28forone count. The sequential counting will continue
until an address is accessed where the bit (U11
pin 15) has been asserted. The bit is asserted in
the waveform memory by the microprocessor at the
address defined by the user as the waveform stop
address. When LOAD goes low, pin 9
(m)
of the
counters is pulled low by U4C. This restarts the address
counters at the start address and therefore restarts the
waveform. An external sync pulse, applied to the Sync
In input will also restart the waveform in the same
Scans by ArtekMedia O 2006