Waveform Latch - Wavetek 75 Instruction Manual

Both RAMs in the waveform memory (U11 and U12)
data based on user input and places that data into the
obtain their power from the battery backed up power userdefined memorylocations.Thedata is thensequen-
supply (BBV). BBV is maintained at 2V or greater even tially accessed to be output to the waveform synthesizer.
when the instrument is turned off. This allows the
waveform memory to retain it's waveform data. When
4.2.1.5
Waveform Latch
the instrument power is off, the output enable (pin 22)
for the RAMs is low. Since the RAMs still have power,
they must be disabled or they will try and drive their data
bus, consuming more power and draining the battery.
The analog switch, U7A and U7B, and it's control line
(m)facilitate this by floating thechipselect lines tothe
RAMs when the instrument power is turned off. This
allows the resistors, R25and R26, to pull thechipselects
(U11 and U12 pin 20) high thus disabling the RAMs.The
switches are controlled by (U7Apin 5)from the power
onloff reset circuit (ref:schematic 01 03-00-1 389 sheet
2). When the instrument power is turned o f f M ~ g o e s low
which opens the switches and the RAMs are disabled.
As the instrument power is turned on,
MR
(U7A pin 5)
is held low. After the microprocessor has stabilized,M~
returns high which then closes the switches in U7 and
allows for normal operation.
As mentioned before, the waveform memory is 8,192
locations deep and 1 6 bits wide. Of these 1 6 bits, the four
least significant in each location are control bits. These
bitsareZBIT(U11 pin 1 I ) , SBIT(U11 pin 12), STBIT(U11
pin 13) and
LO AD
(U11 pin 15). The function of
L O A D
-
is to restart the waveform at the start address. LOAD
is set to a low in the memory location defined by the user
as the waveform stop address. When this location is
-
accessed LOAD causes the waveform address counter
to restart. STBlTis used tostop the waveform in the 'trig-
gered' modes. STBlT is set to a low at locations defined
by the user as breakpoints. It is clocked through the
waveform latch and sent to the Trigger and Hold logic
section. If the instrument is set to a 'triggered' mode,
a low STBlT will cause the trigger logic to stop the
waveform. The Sync Out connector is driven by the con-
trol bit SBIT. This bit is set toa low at the location defined
bythe user as thesyncaddress. SBlTis clocked through
the waveform latch then butfered by U12A and output
to the Sync Out connector (ref: schematic 01 03-00-1 456
sheet 3). ZBlT controls the Z-Axis output. This bit is set
by the microprocessor at locations in waveform memory
where cursors and thumbtacks occur. Its logic polarity
is set by the user. If negative Z logic is selected, ZBlT
is set to a high. If positive Z logic is selected, ZBlTpolarity
is reversed. ZBlT is clocked through thewaveform latch
and sent to the Z-Axis driver circuit (ref:schematic
01 03-00-1 456 sheet 3).
The upper 12 bits of each memory location contain the
waveform data. Of these 12 bits (WBIT1 -WBIT12), WBIT1
is the most significant and WBIT12 is the least signifi-
cant. The microprocessor calculates the waveform
Refer to schematic 0103-00-1456, sheet 3. The main
components of the waveform latch are two octal D type
flip flops. The information present on the D inputs (pins
3,4,7,8,13,14,17 and 18) is transferred to the
Q
outputs
(pins 2,5,6,9,12,15,16 and 19) on the rising edge of the
clock (pin 1 1). The data on the Q outputs is held until the
next clock. The purpose for the latch is twofold. The first
is toensure that the waveform data is valid before being
applied to the waveform synthesizer. When a location
of waveform memory is accessed, the data bits take a
certain amount of time to reach their final state. When
the next clock pulse occurs, the data has become valid
and is clocked through to the waveform synthesizer. The
clock for this circuit is the same clock used in the
waveform address counter. Because of this, the address
for the next waveform memory location is being applied
to the waveform memorywhile the current data is being
latched through to the waveform synthesizer.
The second function of the waveform latch is to allow
the microprocessor to access the waveform memory
without erroneous data being applied to the waveform
synthesizer. When the microprocessor accesses the
waveform memory, ARB RNV (U24Apin 1) goes low. This
clears the flip flop, U24A, and forces pin 5 lowwhich turns
off the clock to the latches. Because the waveform clock
and the microprocessor are running asynchronously it
is possible for pin 5 of U24A to go low in the middle of
a clock pulse. This could result in improper operation of
the latches; i.e. no data latched through or erroneous
data latched through.Toprevent this U17A, U17B, U17C,
U27D, U20B and U22B are configured as a 'whole pulse
circuit'. This circuit assures that if a clock pulse (U27D
pin 13) has started when the clock turn off signal (U24A
pin 5) occurs, the whole pulse will reach the latches
before the clock is shut off. Once the memory access
is finished, ARB RIW (U24A pin 1) goes high.= then
clocks this high through the flip flop to pin 5 which turns
the clock to the latches back on. Once again the 'whole
pulse circuit' assures that only the next complete clock
pulse will reach the latches. NO LOAD (U24A pin 6) is
high when the microprocessor is accessing the
waveform memory. It's function is discussed in
paragraph 4.2.1.2.
The 'nand' gate U20A is used during a return to start.
During normal operation neither GATE (U20A pin 2) nor
BURST(U20Apin 1)are asserted high at thesame time.
When a RETURN is initiated by the user, the micro-
processor sets both of these signals high. This pulls
Scans
by Artekhledia O 2006