Instrument Control; Microprocessor - Wavetek 75 Instruction Manual

toggled mode the burst counter is preset to zero. When "fetch and execute". In a continuously running cycle it
the user accesses the waveform counter, the micro- fetches instructions from read only memory and
processor reads the current count directly and converts executes them. To perform these tasks the micro-
it todecimal for output to the display or communication processor must read from and write to the external
port. When burst mode is selected, the microprocessor circuitry. Each device, or location in a device, that the
must read the counters and calculate the current count microprocessor interfaces to has a unique address. To
before it can be displayed.
access these locations the microprocessor outputs the
The data on the inputs (pins 3,4,7,8,13,14,17 and 18) is
constantly transferred into the latcheson the rising edge
of theclockon pin 11. The outputs(pins 2,5,6,9,12,15,16
and 19) however are in a high impedance state unless
the output enable on pin 1 is low. When the micro-
processor reads the counter value it does so in three read
cycles, accessing each latch one at a time by pulling its
enable (BC1, BC2or BC3) low. Because the counter data
is continuously changing, the clock to the latches must
be turned off when they are being read. Also, the clock
and the enable lines happen asynchronously so that
erroneous data could be transferred across the latches
if the enable occurred in the middle of a clock pulse. To
control the clock, U38A, U48D, U38C, U48A, U48B,
U48C and U38B are configured as a whole pulse circuit.
This circuit ensures that a whole puise is completed
before the clock is turned off. The waveform clock is
applied to this circuit at U48A pin 2. U48D pin 11 is the
"run" control for the circuit. When this is high theclock
is turned on at U48C pin 8 and is turned off when "run"
is low. The enable lines are applied to U38A and when
any one is pulled low the "run" control goes low to turn
off the clock to the latches.
4.2.3 lnstrument Control
4.2.3.1 General Description
Instrument parameters and waveform information are
entered by the user through the front panel, electrical
connectors and the communication port if installed. This
information is processed by the microprocessor and
memory section which in turn controls the appropriate
dedicatedcircuit. Instrument status is reflected back to
the user by the microprocessor and memory section
through the display. The microprocessor and memory
section isdividedfurther intocircuit groups which work
closely with the microprocessor to form essentially one
functional block. These are; power onloff reset, address
decoder, main memory, battery circuit, front panel
interface, control shift register and output ports. A
description of the front panel is included in the front panel
interface.
4.2.3.2 Microprocessor
Refer to schematic 01 03-00-1 389, sheet 2. The basic
operation of the microprocessor can be described as
address and either inputs or outputs the data being
transferred. When data is input to the microprocessor
it is referred to as a read cycle and is called a write cycle
whendata isoutput from the microprocessor. The com-
ponents that make up the functional microprocessor are;
an 8 bit CMOS microprocessor (U30), a 4 MHz crystal
(Yl), an octal 3-state transparent latch (U14), an octal
line driver (U37A and U37B) and two gates of a quad 2
input 'exclusive or' gate (U34A and U34D).
The microprocessor (U30) has an internal clock
generator whose frequency is based on the external
crystal (Yl). Thecrystal frequency of 4 MHz is internally
divided to produce 1 MHz "E" clock on pin 40. The "EM
clock is used as a system clock to synchronize all data
transfers by the microprocessor. The microprocessor
uses a 16 bit address bus and an 8 bit data bus. The lower
8 address bits are time multiplexed with the 8 bit data
bus on pins 37-30. The upper 8 bits of the 16 bit address
bus appear on pins 22-29 (A1 5-A8) of U30. During the
first portion of a read or write cycle, when the
"E"
clock
is low, the lower 8 bits of theaddressbus appear on pins
30-37 (AD7-ADO) and during the last portion of the cycle,
when the "E" clock is high, AD7-ADO are used for the
8 bit data bus. Pin 39 of the microprocessor is the address
strobe (AS). This is a 1 MHz clock whose falling edge is
coincident with the valid address bus on AD7-ADO. The
address latch (U14) is used together with AS to
demultiplex the address and data buses. When a write
or read cycle begins, the full 16 bit address appears on
pins 22-37 of the microprocessor. AS (pin 39)goes high
during this time and the lower 8 bits of the address are
transferred to the outputs of U14 (pins 2,5,6,9,12,15,16
and 19). The address strobe (AS) then goes low and the
lower 8 bits of the address bus are latched into U14.
AD7-ADO are used for data bus transfer for the rest of
the cycle.
The Iineon pin 380f the microprocessor is the readlwrite
control
(Rim)
where a high indicates a read and a low
indicates a write. It is used by the external devices to
determine if the microprocessor is executing a read
cycle or a write cycle. ' T he "EM clock, AS and
RI W
are
gated together to create the various enable signals and
synchronize bus timing for the external devices interfac-
ing with the microprocessor. A diagram of the bus tim-
ing for the microprocessor is shown in figure 4-7. An
inverted version of the readlwrite control called Rlw is
created by the "inverter" U2D and is used in the main
Scans by Artekhledia O 2006