Trigger And Hold Logic; Frequency Ranging; Mode Control - Wavetek 75 Instruction Manual

Table 4-2. Frequency Ranging
Sample
Frequency Range
2 MHz
-
200 kHz
199.98 kHz
-
20 kHz
19.998 kHz
-
2 kHz
1.9998 kHz
-
200 Hz
199.98 HZ
-
20 HZ
19.998 HZ
-
2 Hz
1.9998 Hz
-
200 mHz
199.98 mHz
-
20 mHz
4.2.2.3 Trigger and Hold Logic
'Refer to schematic 01 03-00-1 456, sheet 3. The trigger
and hold logic can be broken up intocircuit blocks. These
are; reference selector, whole pulse circuit, trigger and
mode control, and miscellaneous 110.
The reference selector is made up of three "inverters"
(U12D, U25E and U25D)and three 2 input "nand" gates
(U16C, U26Cand U21C).-The internal reference from the
frequency synthesizer is applied to this circuit on pin 9
of U25D (INTREF). Any external reference frequency
applied to the Ref In connector appears at U12D pin 9
(REF IN). As with all digital inputs Ref In is protected
against overvoltage by diodes, in this caseCR3 and CR4.
The microprocessor determines which signal is used
with the line REFSEL(U25E pin 1 l).This line is interfaced
to this circuit from the control shift register (ref:
schematic 01 03-00-1 456 sheet 2). When REFSEL is high
the internal reference frequency is gated through U26C
and appears on U21C pin 8. To select the external refer-
ence frequency, the microprocessor sets REFSEL low.
' T he whole pulsecircuit turns the waveform clockon and
off. Itconsistsofthree 2input "nand"gates(U16A. U16D
and U16B), one 3 input "nand" gate (U22A) and two
"exclusive or" gates (U15A and U15D). The reference
frequency is applied to this circuit on pin 1 of U15A. U16A
pin 1 is considered the "run" control. When the "run"
is high the reference frequency passes through the cir-
cuit to U15D pin 11 (CLK). When "run" is low the refer-
ence frequency is blocked and CLK is off. Because the
"run" control and the reference frequency are running
asynchronously, "run" can change states in the middle
of a clock pulse. The resulting narrow pulse would
adversely effect the circuitry driven by the waveform
pin 13) is used by the microprocessor to manually drive
the waveform clock. During a RETURN, the micro-
processor asserts MANHOLD (U27B pin 4) to stop the
waveform clock and then pulses PCLK to clock the
waveform memory through the return ramp.
The trigger and mode control consists of three D flip flops
(U24B, U23Aand U23B) and the logic gates surrounding
them. This circuit is controlled by the mode information
from the microprocessor and the trigger inputs, both
manual and external. The mode control bits originating
at the microprocessor are;
m,
GATE, TGL, and
BURST. These control lines are interfaced to this circuit
f r o m the c o n t r o l shift register (ref: schematic
01 03-00-1 456 sheet 2). The truth table for the mode con-
trol bits is shown in table 4-3.
BURST
U21-12
Table 4-3. Mode Control
Continuous
Triggered
Gated
Toggled
Burst
CONT
Mode
Low
High
High
High
High
Low
Low
High
High
Low
GATE
U21-4
Low
Low
Low
High
Low
I
TGL
U15-9
Low
Low
Low
Low
High
The function of the trigger section is to control the "run"
signal to the whole pulse circuit which in turn controls
the waveform clock (CLK). In continuous mode, CONT
(U23B pin 10) is held low. This sets the flip flop U23B
which pulls the Q (pin 8) of U23B low and turns on the
waveform clock (CLK). When triggered mode is selected,
CONT is set high. The next waveform clock pulse clocks
the high through U23A which clears U23B and sets its
-
Q(pin 8) high. With that line high, the break points in the
waveform memory are used to stop the waveform clock
by driving U26B pin 4. The flip flops of U23 are immedi-
ately reset to wait for a trigger pulse on the clock input
(pin 1 1) of U23B. When a break point is encountered in
the waveform memory, STOP(U1 pin 15, ref: schematic
01 03-00-1456 sheet 3; waveform latch) is pulled low.
-
STOP is gated with NO LOAD at U15D (ref:schematic
01 03-00-1 389 sheet 3) to set TPOINT high. NO LOAD
inhibits accidental break points when the micro-
processor is accessing the waveform memory. TPOINT
(U22Cpin 1l)forces U26Bpin4 high which turnsoff the
waveform clock (CLK).
clock (CLK). The whole pulse circuit prevents this by When a trigger pulse is applied to theTrig In connector,
allowing the clock to finish its current pulse before it is
it is gated through U12B, U15B, U15C, U26D, and U26A
shut off. The resistor on pin 12 of U22A and all the
so that a positive pulse appears at the clock input of
resistors in RN3 serve as pull up resistors to interface U23B. Since the D input (pin 12)is high, theaoutput (pin
logic levels between different logicfamilies. PCLK(U15D
8) is pulled low which turns on the waveform clock until
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