Waveform Address Selector; Waveform Memory - Wavetek 75 Instruction Manual

manner. The PLOAD input to UIOC is used by the
microprocessor to force the waveform memory to a
specific address during a return to start. The NO LOAD
input to U35C originates from the waveform memory con-
trol circuitry. Whenever the microprocessor reads from
or writes to the waveform memory, NO LOAD goes high
and blocks the reloading of the address counters. This
prevents accidental restarting of the waveform if LOAD
is pulled low during the microprocessor's access of the
waveform memory. All locations in the unused portions
7
of the waveform memory have LOAD asserted. This
ensures that the waveform will restart even if the
microprocessor is accessing the waveform memory
when the stop address occurs.
4.2.1.3 Waveform Address Selector
Refer to schematic 0103-00-1389, sheet 3. 'The
waveform address selector consists of four quad 2-input
data selectors (U29, U19, U18 and U23). These data
selectors determine whether the location in the
waveform memory to be accessed is under the control
of the address counters or the microprocessor. When
the waveform is running, U1OA pin 12 is high thus
selecting the 'B' inputs to the data selectors. This con-
nects the outputs of the waveform address counter to
the address bus of the waveform memory. When the
microprocessor is accessing the waveform memory,
ARBMEM (U5B pin 12) goes low. AS (U2C pin 5) then
clocks this low through the flip flop U5B, setting U5B pin
8 high. This forces U1OA pin 12 low, selecting the 'A'
inputs to the data selectors. This connects a portion of
the microprocessor's address bus (ADR13-ADR1 )to the
waveform memory address bus. The microprocessor is
then able to write to or read from any location in the
waveform memory. ARBMEM originates in the address
decoding section of the microprocessor. AS (address
strobe) is a continuously running output of the micro-
processor. The signal labeled SELOVR is an output of
the microprocessor section. When a return to star! is
initiated by the user, the waveform is held at its current
address. SELOVR holds the address select line (U1 O A
pin 12) high and maintains the waveform memory at the
location determined by the addresscounter. The micro-
processor can then read the current data in the
waveform memory in order to calculate a ramp back to
the starting value.
4.2.1.4 Waveform Memory
Refer to schematic 01 03-00-1 389, sheet 3. The main com-
ponents of the waveform memory are two rando; access
memories (U11 and U12) and two octal bus transceivers
(U16 and U17). The random access memories (RAM) each
contain 8,192 memory locations with each location 8 bits
wide. The location to be accessed is determined by the
13 bit binary number on the RAM address bus (A1 2-AO).
If data is to be written into the RAM, pin 27(Write Enable)
is pulsed low. If data is to be read from the RAM, pin 22
(Output Enable) is pulsed low. The chip select (pin 20)
must be low to enable any activity to the RAM. The bus
transceivers act as two way gates between the wave-
form memoryand the microprocessor'sdata bus. When
U16 pin 19 (EN) is high, the transceiver enters a high
impedance state and no data is transferred through it.
When pin 19 (EN) is low, the direction of data transfer
is determined by pin 1 (DIR). If pin 1 (DIR) is high, data
is transferred from the 'A' side to the 'B' side. When pin
1 is low, the direction of transfer reverses.
The waveform memory is setup in a '2 port' configura-
tion. From the microprocessor's point of view, the
waveform memory appears as one RAM that is 16,384
locationsdeep by 8 bits wide. In this configuration, U12
contains all the even numbered locations and U11 con-
tains all the odd numbered locations. To the waveform
synthesizer the waveform memory appears as one RAM
that is 8,192 locations deepby 16 bits wide. The four least
significant bits are used for control and the upper 12
(WBIT12-WBITI) are the waveform data bits.
The microprocessor accesses the waveform memory
for several reasons; to fill it with waveform data, to read
or change waveform data at a gpecific location or to set
the control bits. To write toor read from one 16 bit wide
waveform memory location,the microprocessor must
execute two 8 bit write or read cycles. When the micro-
processor accesses the waveform memory, ARBMEM
(U5B pin 12) goes low. AS (U2C pin 5) clocks this low
through the flip flop U5B which sets pin 9 low. Thus, the
stateof the chip selects for the waveform memory RAMS
(U15A pin 1 and U15B pin 4) depend upon ADRO (U8A
pin I ) , which is the least significant bit of the micro-
processor address bus. When an even numbered
-
memory location is addressed, ADRO is low setting CSO
(U15Apin 1) low and enabling U12. S i n c e m l (U15B pin
4)is high at this time, U17isalsoenabled. If this isawrite
cycle m W (U5A pin 2 and U17 pin 1) is high. Data
(AD7-ADO)(U30) then flows through U17 from the micro-
processor to U12. This also sets
AWE
(U4A pin 3) low
which causes U12 to accept data. If an odd numbered
memory location is being addressed, the same sequence
occurs except U8A Pin 1 (ADRO) is high selecting U11
and U16. During a read cycle,R/W is low. This changes
the direction of transfer through U16 and U17 and sets
AOE
(U6A pin 3) low which forces the selected RAM to
output data. The two lines,
E
(U3D pin 12) and EB (U4A
pin 2) are continuously running signals that originate in
the microprocessor section. They are used to syn-
chronize data transfer during read and write cycles.
Waveform memory read and write timing is shown in
Figure 4-2A and B.
Scans by A 1