Address Decoder; Microprocessor Address Map - Wavetek 75 Instruction Manual

During normal operation the RESET line (pin 6) is held
high by the resistor R4. When the power is turned off,
U30 pin 6 is again pulled low before the falling power sup-
plies disrupt microprocessor operation. The reset tim-
ing is shown in figure 4-8.
When the instrument power is turned off, the power
onloff reset circuit pulls the STBY input of the micro-
processor low (U30 pin 7). This forces the micro-
processor into a low power standby mode before the
battery becomes its sole power source. In this way
battery life is extended. The timing for the STBY control
is shown in figure 4-8.
The microprocessor used has several operational
modes. The Model 75 uses what is called mode 2. This
mode uses the multiplexed address and data bus as
described earlier. The mode used is determined by the
status of pins 8, 9 and 10 of U30 during the power up
sequence. Pin 9 is permanently tied to +5V and is
unused during normal operation. The resistors R13 and
R14 hold pins 8 and 10 low during power up and are
large enough to allow the use of these pins as outputs
during normal operation. The timing for the mode selec-
tion is shown in figure 4-8.
4.2.3.3 Power OnlOff Reset
Refer to schematic 01 03-00-1 389, sheet 2. The power
onloff reset circuit consists of three voltage com-
parators (U20A, U20C and U20D) and resistor voltage
dividers to set thresholds. The comparator, U20D, con-
trols the reset line
(m)
during power up and U20C con-
trols the power off reset. The comparators have open
collector outputs which can only pull their outputs low.
The outputs are wire or'd together and pulled up by the
resistor R4. When the instrument is turned on, the
+
5V
supply pulls the voltage on the inverting input of U20D
(pin 10) to a voltage determined by the voltage divider
of R12, R8 and R6. The voltage on the noninverting
input of U20D (pin 11) is pulled up at a much slower
rate since the capacitor, C4 must be charged. While
the voltage at pin 11 is lower than the voltage at pin
10 the comparator pulls
M
low. Once C4 has charged
to a voltage greater than the threshold on pin 10,
MR
is released and pulled high by R4. When the instrument
is turned off the sequence is very similar. The
+
5V
supply on the noninverting input of U20C (pin 9) drops
rapidly while the voltage on the inverting input (pin 8)
is held by the discharging C4, causing the comparator
to pull
m
low.
The comparator, U20A, controls the standby pin on the
microprocessor. This line is held high by the resistor
R3 during normal operation. When the instrument is
turned off, the
+
5V supply on the noninverting input
(pin 5) falls below the voltage on the inverting input
(pin 4) set by the zener diode, CR1. This causes the
comparator to pull
MR
low. The timing for the power
onloff reset and standby control is shown in figure 4-8.
4.2.3.4 Address Decoder
Refer to schematic 01 03-00-1 389, sheet 2. All devices
that interface with the microprocessor are assigned a
unique address location. Devices that contain more
than one location, memories for example, are assigned
a block of addresses. When the microprocessor
accesses a location, it outputs the 16 bit address of
that location onto the address bus (ADRl5-ADRO). It
is the job of the address decoder to determine which
location or block of locations is being accessed and
enable that device. The address map in table 4-4 shows
the address assignments for these peripheral devices.
The main components of the address decoder are three
1 of 8 decoders (U9, U13 and U27) and miscellaneous
logic gates. Each decoder has three chip select inputs
(pins 4,5 and 6) and three address select lines (pins 1,2
and 3). Of the chip select inputs, G I must be high, and
G2A and G2B low, to enable the decoder. When the
decoder is enabled, the 3 bit binary number on its select
lines determines which output is active. The Y7-YO out-
puts are active low.
Table 4-4. Microprocessor Address Map
Addressable Devices
Internal Registers
Internal RAM
Output Port 0
Output Port 1
Output Port 2
Output Port 3
Output Port 4
lnput Port 1
lnput Port 2
RKlRQ (Reset Knob
Interrupt)
BC3 (Burst Count
Read)
BC2 (Burst Count
Read)
BC1 (Burst Count
Read)
Display
Communication Port
RAM
Waveform Memory
ROM
1
Address
1
(Hexadecimal) Size
32 bytes
128 bytes
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
2 bytes
8 bytes
8K bytes
16K bytes
32K bytes
Scans by ArtekMedia O 2006