Mechanical Data; Packaging; Pin Assignment - Intel 80960SA Manual

Embedded 32-bit microprocessor with 16-bit burst data bus
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3.0

MECHANICAL DATA

3.1

Packaging

The 80960SA is available in two package types:
80-lead quad flat pack (EIAJ QFP). Shown in
Figure 15.
84-lead plastic leaded chip carrier (PLCC).
Shown in Figure 16.
Dimensions for both package types are given in the
Intel Packaging handbook (Order #240800).
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
V
65
SS
66
ALE
67
READY
68
A31
69
A30
70
A29
71
A28
72
V
SS
73
V
CC
74
A27
A26
75
A25
76
V
77
CC
V
78
SS
79
A24
80
A23
1
2 3 4
Figure 15. 80-Lead EIAJ Quad Flat Pack (QFP) Package
NOTE: To address the fact that many of the package prefix variables have changed, all
package prefix variables in this document are now indicated with an "x".
x80960SA-20
XXXXXXXX
XXXXXX
XXXXXX
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21
3.2

Pin Assignment

The QFP and PLCC have different pin assignments.
The QFP pins are numbered in order from 1 to 80
around the package perimeter. The PLCC pins are
numbered in order from 1 to 84 around the package
perimeter. Tables 9 and 10 list the function of each
QFP pin; Tables 11 and 12 list the function of each
PLCC pin.
V
and GND connections must be made to multiple
CC
V
and GND pins. Each V
CC
connected to the appropriate voltage or ground and
externally strapped close to the package. It is recom-
mended that you include separate power and ground
planes in your circuit board for power distribution.
Pins identified as NC (No Connect) should never be
connected
.
22 23 24
80960SA
and GND pin must be
CC
40
BE1
39
NC
38
A1
37
V
SS
36
V
CC
35
A2
34
A3
33
V
CC
32
V
SS
31
D0
30
AD1
29
AD2
28
AD3
27
AD4
26
AD5
25
AD6
21

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