Table of Contents
Advertisement
Table 3. 80960SA Pin Description: Bus Signals (Sheet 2 of 2)
NAME
TYPE
LOCK
I/O
BUS LOCK prevents bus masters from gaining control of the bus during
O.D.
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. If the pin is
already asserted, the processor waits until it is not asserted. If the pin is not
asserted, the processor asserts LOCK during the T
The processor deasserts LOCK in the T
is asserted, a bus agent can perform a normal read or write but not a RMW
operation. The processor also asserts LOCK during interrupt-acknowledge transac-
tions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
ONCE MODE: The LOCK pin is sampled during reset. If it is asserted LOW at the
end of reset, all outputs will be three-stated until the part is reset again. ONCE
mode is used in conjunction with an in-circuit emulator.
BE1:0
O
BYTE ENABLE LINES specify which data bytes (up to two) on the bus take part in
T.S.
the current bus cycle. BE1 corresponds to AD15:8; BE0 corresponds to AD7:1, D0.
The byte enable lines are asserted appropriately during each data cycle.
INITIALIZATION FAILURE indicates that the processor has failed to initialize
correctly. The failure state is indicated by a combination of BLAST asserted and
BE1:0 not asserted. This condition occurs after RESET is deasserted and before
the first bus transaction begins. FAIL is asserted while the processor performs a
self-test. If the self-test completes successfully, FAIL is deasserted. The processor
then performs a zero checksum on the first eight words of memory, If it fails, FAIL is
asserted for a second time and remains asserted; if it passes, system initialization
continues and FAIL remains deasserted.
HOLD
I
HOLD indicates a request from an external bus master to acquire the bus. When
the processor receives HOLD and grants bus control to another master, it floats its
three-state bus lines, then asserts HLDA and enters the T
deasserted, the processor deasserts HLDA and enters the T
HLDA
O
HOLD ACKNOWLEDGE notifies an external bus master that the processor has
T.S.
relinquished control of the bus. This signal is always driven. At reset it is driven
LOW.
BLAST/FAIL
O
BURST LAST indicates the last data cycle (T
T.S.
during the last T
INITIALIZATION FAILURE indicates that the processor has failed to initialize
correctly. The failure state is indicated by a combination of BLAST asserted and
BE1:0 not asserted. This condition occurs after RESET is deasserted and before
the first bus transaction begins. FAIL is asserted while the processor performs a
self-test. If the self-test completes successfully, FAIL is deasserted. The processor
then performs a zero checksum on the first eight words of memory, If it fails, FAIL is
asserted for a second time and remains asserted; if it passes, system initialization
continues and FAIL remains deasserted.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
DESCRIPTION
cycle of the write transaction. While LOCK
a
and associated with T
cycles in a burst access.
d
w
cycle of the read transaction.
a
state. When HOLD is
h
or T
state.
i
a
) of a burst access. It is asserted low
d
80960SA
9
Advertisement
Table of Contents
