Table of Contents
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Symbol
Parameter
Input Clock
T
Processor Clock Period (CLK2)
1
T
Processor Clock Low Time (CLK2)
2
T
Processor Clock High Time
3
(CLK2)
T
Processor Clock Fall Time (CLK2)
4
T
Processor Clock Rise Time (CLK2)
5
Synchronous Outputs
T
Output Valid Delay
6
T
AS Output Valid Delay
6AS
T
ALE Width
7
T
ALE Output Valid Delay
8
T
Output Float Delay
9
Synchronous Inputs
T
Input Setup 1
10
T
Input Hold
11
T
Input Setup 2
12
T
Setup to ALE Inactive
13
T
Hold after ALE Inactive
14
T
RESET Hold
15
T
RESET Setup
16
T
RESET Width
17
NOTES:
1. Processor clock (CLK2) rise time and fall time are not tested.
2. A float condition occurs when the maximum output current becomes less than I
no longer than the valid delay.
3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by using AS.
Table 7. 80960SA AC Characteristics (16 MHz)
Min
31.25
8
8
2
2
T
- 11
1
2
2
10
2
13
10
8
3
5
1281
Max
Units
125
ns
V
= 1.5V
IN
ns
V
= 10% Point
T
= V
CL
ns
V
= 90% Point
T
= V
CL
10
ns
V
= 90% to 10% Point (1)
T
10
ns
V
= 10% to 90% Point (1)
T
25
ns
21
ns
ns
22
ns
20
ns
(2)
ns
ns
ns
ns
ns
ns
(3)
ns
(3)
ns
41 CLK2 Periods Minimum
. Float delay is not tested, but should be
LO
80960SA
Notes
+ (V
– V
) x 0.1
CH
CL
+ (V
– V
) x 0.9
CH
CL
17
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