1. Explanation of Product 1-1. System Overview The MP-2000 series are Casio’s new PC based POS system. The MP-2000 equip 9.4 inch LCD display and 84 soft keyboard. MP-2000 (CPU module) COVER-2 (optional) Accessories 1. FDD External cable 1 pc 2.
(Separately provided) 1-2. Unpacking The MP-2000 along with its accessories are packed in carton boxes. Make sure that all of the items listed in previous page are present. After unpacking the cartons, place the system on a raised surface and carefully inspect the system for any damage that might have occurred during shipment.
1-3. Installation For Installation for LCD display module (MODEL MP-2060DP), it is necessary to instal the BIOS chip and LCD control board to the CPU module as showing the following steps. 1. Open the upper cover of CPU module. 2. Release the 4 screws for the insulation sheet and the Alminum separator.
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Close the upper cover to the CPU module. NOTES: 1. The MP-2000 CPU module do not equip any operating system. An operating system must be loaded first before installing any software into the MP-2000 CPU module. 2. Be sure to ground yourself to keep from any static charge when you install the internal components.
MP-2000 system, for instance, Dual Display function, ACPI green function and so 2) The system Bios that is installed in the standard MP-2000 does not support the MP-2060DP LCD display. Please change the chip that is packed in the MP-2060DP in case to use the MP- 2060DP together with the MP-2000.
1-5. I/O Outlet < Bottom Panel > FD D M OU S E K/ B LC D DRW 2 DRW 1 P R N COM 4 COM 3 COM 2 COM 1 V G A N E T 1 External FDD 7 Parallel port 2 2 x Cash drawers 8 4 x COM ports( COM 1, 2, 3 and 4 )
2. Model List Model Name Description Note MP-2000 CPU module For USA, Canada, UK, and Germany MP-2000S CPU module For countries other than above MP-2040KY Keyboard 84 Key module MP-2041KY Large Keyboard Large Key module MP-2060DP LCD module Mono-LCD unit...
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4. Release the screw. Then, remove the upper cover from front side. 5. Release the 2 screws of the Riser card. Then, remove the Riser card from the mother board. Release 2 screws. 6. Release the 4 screws of the Aluminum separator. Then, remove the insulation sheet and Aluminum separator.
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7. Release the 4 screws of the LCD control board (Option item). Then, remove the LCD control board. Release 4 screws. LCD control board is option item. 8. Release the 4 screws of the HDD fixing plate. Then, remove the HDD fixing plate with HDD.
* System O/S and Software Installation The MP-2000 has a Pentium little board with a free PCI/ISA slot inside. It already builds in a Pentium CPU, 16MB of DRAM and a 2.5" HDD. These are all standard and the system is ready to play. Variety of the I/O ports located at the back side of the chassis are available for customers to connect external peripheral devices, such as a monitor, serial devices, parallel printer..
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1 and pin 9, ready to accommodate a wide array of serial devices. COM1 to COM4 are all D-SUB 9-pin connec- tors. In this case the COM2 for the MP-2000 is to set to RS-422/485, the related jumpers have to be set correctly.
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Not use Cash Drawer The MP-2000 provides two Cash Drawer interface. Cash Drawers are assigned as one of I/O in this system and controlled by the Digital I/O port on the motherboard (SBC8352). The pin assignment for the Cash Drawer connector is as follows.
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External FDD The MP-2000 does not build in any floppy disk drive into the main system. Rather, it provides a FDD interface located at the side panel. An external FDD cable is provided to connect a standard 3.5" FDD to the system for system O/S and application software installation.
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Expansion Slot The MP-2000 provides a free PCI/ISA + PCI expansion slot to accommodate either an ISA or PCI device at a given time. The expansion card can be plugged into the riser card which is plugged in the onboard PCI/ISA slot as standard.
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BIOS Setup AMI BIOS Setup Starting AMI BIOS Setup As POST executes, the following appears: Hit <DEL> if you want to run SETUP Press <Del> to run AMI BIOS Setup. AMI BIOS Setup Main Menu When you enter the AMI BIOS Setup Utility, the main menu will appear on the screen as follows. Use the arrow keys to move among the items and press <Enter>...
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Setup The AMI BIOS Setup options described in this section are selected by choosing the appropriate high-level icon from the AMI BIOS Setup main menu selection screen. Default setting for the QT-7100 is described in < > next to each option. ( i.e. <AUTO> ) [Standard CMOS Setup] When entering this item, the following screen will be shown;...
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[Advanced CMOS Setup] Boot Device < 1 : FLOPPY, 2 :IDE-0, 3 :CDROM, 4 :Disabled > This option sets the sequence of boot drives either floppy drive A or hard disk drive C or CDROM that AMI BIOS attempts to boot from after POST completes. Floppy Drive Swap <...
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Wait for <F1> If Any Error < Enable > AMI BIOS POST runs system diagnostic tests that can generate a message followed by Press <F1> to continue Enable : AMI BIOS waits for the user to press <F1> before continuing. Disabled : AMI BIOS continues the boot process without waiting for <F1>...
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[Peripheral Setup] Onboard FDC This option enables the use of the built-in floppy drive controller. The setting is Auto, Enabled or Disabled . OnBoard Serial Port 1 <3F8h, IRQ4> NOTE: Do not change this setting, since COM1 is assigned for the touch screen. It may cause system problem.
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PCI/Plug and Play Setup POWER MANAGEMENT Setup — 21 —...
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[Watchdog Function] The MP-2000 features a system protective device, watchdog timer which can generate a CPU reset when the system comes to a halt or failure. This function is to ensure the system’s reliability during unattended operation. The trigger sources for the watchdog contain both temperature over range and system failure. The system failure may be caused by thunder, power glitch, radio interference, software bug or whatever reason.
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LCD display LCD display (MP-2060) Specification Model MP-2060DP Display Type MonoLCDdisplay Panel Size 9.4" Max Resolution 640x480 Colors 32 Gray scale S/W Drivers Before you begin the driver software installation, be sure to make backup copies of the Display Driver Diskettes. Make sure you know the version of the application for wich you are installing drivers.
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VGA Software Utilities DOS Utility These utility programs are designed to work with MS-DOS. MODETEST MODETEST is a DOS based diagnostic tool to set and display information for each video mode. To execute the MODETEST utility program, type the following command: MODETEST All the VGA modes will be sequentially displayed by pressing <ENTER>.
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75 Hz 85 Hz NOTE: The refresh rates that are supported by the selected monitor are the only refresh rates that will show and be selectable. The above Refresh Rates may not be supported by all CHIPS products. WINDOWS DEFAULT allows you to return to the default refresh rate setting for the selected monitor in Windows Setup Programs The following setup programs were developed for the installation of CHIPS Display Drivers through Windows or DOS.
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Following software are provided in the floppy disk (Disk 4) for setup and test the Ethernet system. The Setup Program The MP-2000’s Ethernet can be either set to PnP or non-PnP modes. In non-PnP mode, the configuration is accompanied by the execution of the setup program, “SETUP.EXE”. After passed a series of tests, the following screen will appear: UM9008 PnP Ethernet Controller Configuration &...
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Automatic Detection This function is used to change different modes, including Jumper-less, Automatic detect and PnP modes and automatically configure the onboard Ethernet with available IRQ and I/O settings. To modify these settings, the “Modify configuration” has to be selected. Installing Network Driver ( Windows 95, Windows 98 or Windows NT) select Add new hardware.
1-2, JP10 (2) Multi I/O Board (MP-2000) The default setting of the Multi I/O Board for MP-2000 are as follows: Multi I/O Board Jumper Setting (Default) J P 4 , 5 , 6 , 7 J P 1 , 3 JP No.
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The following tables show the specification of the jumper settings. < * : Default / X : Don’t Care > Note: All specification and quality of the system are assured by Casio as the MP-2000, any local modification of the jumper setting by customer will not be applicable for Casio’s guarantee or warranty.
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+5V/+12V/+24V power capabilities on both Pin 1 and Pin 8, ready to accommodate a wide array of serial devices. The corresponding jumper settings are shown below. < SBC8352 means the motherboard and MTIO means the Multi I/O board in the MP-2000. > COM1:Pin 1...
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COM2:Pin 9 SBC8352 MTIO JP15 JP16 JP19 8-10* (3-5,4-6,9-11,10-12)* 5-6* 1-2* 1-2* 4-6* Normal COM/RS232 8-10 (1-3,2-4,7-9,8-10) Normal COM/RS422 8-10 (1-3,2-4,7-9,8-10) Normal COM/RS485 (3-5,4-6,9-11,10-12) +12V (3-5,4-6,9-11,10-12) +24V (3-5,4-6,9-11,10-12) COM3:Pin 1 SBC8352 MTIO JP18 Normal COM 7-9* 1-2* 1-2* 3-5* +12V +24V COM3:Pin 9 SBC8352...
Use the following softwares for checking each block. Mother board ........AMI Diag.5.42 (available in the market) Customer display ........ Diagnostic program built in the QT-7060D,7062D,7063D. Drawer ..........drw.exe (available from Casio) 6-2. Customer display Necessary tools Loop back connector...
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In case of QT-7063D Loop back connector Display signal connector AC adaptor jack 1 Connect a loop back connector on Customer display stand unit. 2 Connect a testing customer display to Display signal connector. 3 Apply +24V DC to the AC adaptor jack. PRINTER Female HOST...
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Precautions 1 For checking QT-7063D, use customer display stand unit. 2 Turn the power off before connecting the customer display. 3 After the check, be sure to set the DIP switch correctly. 4 Also check rotating mechanism of the customer display. Diagnose Screws 1 Unscrew four screws and remove display panel.
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All dots off All dots on A vertical line moves from right to left. 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 — 36 —...
7. Troubleshooting This portion of the service manual lists all possible malfunctions that may occur when operating the MP-2000 system. To assist you in fully analyzing the problem, the following table also includes an up-to-date list of symp- toms and probable cause(s). In case you encounter problems or discover causes not included in this section, we highly recommend you to consult CASIO engineers.
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– Loose power connection on CN2 of the touchscreen control board. properly Pull out the power cable on CN2 then re-install it back. If symptoms persist, consult CASIO engineers. – Defective touchscreen control board Replace the touchscreen control board of the system.
8. Data Sheet 65550 (HiQV32TM) High Performance MultiMedia Flat Panel/CRT GUI Accelerator M5113 Enhanced Super I/O Controller with plug & play UM9008 ISA/plug & play super Ethernet Controller VT82580 Geen Pentium/P54C/M1/K5 PCI/ISA System with unified memory architecture, Universal serial Bus and Master mode PCI-IDE Controller VT82C585VP System Controller VT82C586VP...
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CPU Direct / VL-Bus Interface Pin names in parentheses (...) indicate alternate functions. Pin # Pin Name Type Active Description RESET Reset For VL-Bus interfaces, connet to RESET For direct CPU local bus interfaces, connect to the system reset generated by the motherboard system logic for all periph- erals (not the RESET# pin of the processor).
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Pin # Pin Name Type Active Description High System Address Bus. In VL-Bus, and direct CPU inter- High faces, the address pins are connected directly to the bus. High In internal clock synthesizer test mode (TS# = 0 at Reset). High A24 becomes VCLK out and A25 becomes MCLK out.
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Bus Output Signal Status During Standby Mode 65550 Pin# Signal Name Signal Status ACTI / A26 Driven Low ENABKL / A27 Driven Low LRDY# / RDY Tri-Stated LDEV# Tri-Stated 51-44, 41-40, 38-33 D0 - 15 Tri-Stated 20 -13, 8 -1 D16 -31 Tri-Stated PCI Bus Interface...
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Pin # Pin Name Type Active Description STOP# S/TS Stop. Indicates the current target is requesting the master to stop the current transaction DEVSEL# S/TS Device Select. Indicates the current target has decoded its address as the target of the current access PERR# (VCLKOUT) S/TS Parity Error.
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Pin # Pin Name Type Active Description AD00 High PCI Address / Data Bus AD01 High Address and data are multiplexed the same pins. A bus AD02 High transaction consists or an address phase followed by one or AD03 High more data phases (both read and write bursts are allowed by AD04 High...
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Pine Pin Name Type Active Description CA0 (P16) High Address bus for DRAM C (P17) High CA2 (P18) High CA3 (P19) High CA4 (P20) High CA5 (P21) High CA6 (P22) High CA7 (P23) High CA8 (BLANK) Hi/Lo CA8 may be configured as VAFC BLANK# out or vertical reference input (VREF) for video capture.
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Pine Pin Name Type Active Description MBD0 High Memory data bus for DRAM B (upper 5I2KB) MBDI High MBD2 High MBD3 High MBD4 High MBD5 High MBD6 High MBD7 High MBD8 High MBD9 High MBD10 High MBD11 High MBD12 High MBD13 High MBD14...
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Flat Panel Display Interface Pin # Pin Name Type Active Description High 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit High panel interfaces may also be supported (see CA0-7 for P16. High 23). High High Refer to the table on the next page for the configurations for High various panel types.
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Color Mono Mono Mono Color Color Color Color Color Color Color 65550 TFT HR STN SS STN SS STN DD STN DD STN DD 9/12/16 18/24 18/24 8-bit 16-bit 8-bit 16-bit Pin# 8-bit 8-bit 16-bit 24-bit Name (X4bp) (4bp) (4bp) (4bp) –...
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CRT & Clock Interface Pin # Pin Name Type Active Description HYSNC (CSYNC) Both CRT Horizontal Sync (polarity is programmable) or “Composite Sync” for support of various external NTSC/ PAL encoder chips. Note CSYNC can be set to output on the ACTI or ENABKL pins.
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CRT/ PANEL Signal Status During Standby Mode 65550 Pin# Signal Name Signal Status Driven Low (weak) Driven Low (weak) SHFCLK Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak) Driven Low (weak)
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Display Memory Output Signal Status During Standby Mode 65550 Pin# Signal Name Signal Status RASA# Driven Low RASB# Driven Low RASC# Driven Low (see note below) WEA# Driven High WEB# Driven High WEC# Driven High (see note below) CASAL# Driven Low CASAH# Driven Low CASBL#...
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Power/ Ground and Standby Control Pin # Pin Name Type Active Description STNDBY# Standby Control Pin. Pull this pin to place the chip in Standby Mode. Power / Ground (Internal Logic). 5V ±10% or 3.3V ±0.3V. IVCC IGND Note that this voltage must be the same as CVCC (voltage for internal clock synthesizer).
8-2 M5113 : Enhanced Super I/O Controller with Plug & Play Supports Windows 95 Plug and Play Enhanced ESD/LATCH up to over 4KV/300 mA Supports SPP, PS/2, EPP and ECP parallel port Enhanced UART (16550) Supports IR from UART1, UART2 and two additional IR pins Single-chip Notebook/Desktop solution Supports 2.88-MB/1.44-MB/1.2-MB/720-KB/360-KB FDD formats Supports Windows 95 Plug and Play...
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Pin Description The following table lists the functions of all M5113 pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4v nominal). Name Number Type Description HOST Processor Interface D0-D7 18-51, 53-56 I/O24 Data bus.
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Name Number Type Description Floppy Disk interface WDATAJ Write Data. This active low output is a write- precompensated serial data to be written onto the selected disk drive. Each falling edge causes a flux change on the media. HDSELJ Head Select. This active low output determines which disk drive head is active. Low=Head 0, high (open) = Head 1.
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Name Number Type Description RTS1J Request to send. Active low Request to send output for Primary Serial port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR).
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Name Number Type Description RI1J, RI2J 84, 86 Ring Indicator. This active low input is for primary and secondary serial ports. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of RIJ signal by reading bit 6 of Modem Status Register (MSR).
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Name Number Type Description IRTX2 Alternate IR Transmit output. IRRX2 Alternate IR Receive input. FACF Floppy Disk Address Control. This signal is read and latched during reset active. UR21RQB I/O24 Serial Port Interrupt Request. Alternate IRQ output from UART2, refer to CR0 bit 5.
8-3 UM9008: ISA/Plug & Play SuperEthernet Controller Features Single chip solution for IEEE 802.3. 10BASE-T, Provide 10BASE-T transceiver and Attachment Unit 10BASE2 and 10BASE5 Interface (AUI) auto detect and auto-Switch function Integrated ISA interface, 8Kx16 SRAM, Media Access Control. ENDEC, and 10BASE-T transceiver External EEPROM programmable Support ISA Plug and Play configuration function Support BOOT ROM page mode...
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Pin Description Pin No. Symbol Description PC ISA BUS INTERFACE PINS 96-99 SA0-SA3 SYSTEM ADDRESS: These signals are connected to the address SA4-SA6 bus of the PC I/O slot. They are used to select the UM9008 I/O ports or the boot ROM address 11-13 SA9-SA11 15-18...
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Pin No. Symbol Description 64-71 MD0-MD7 I/O, Z MEMORY DATA BUS: These are the memory data signals for the boot ROM When the EEPROM is loaded or written, MD0, 1, 2 are used as the EEPROM signals (64) (EED1) • EEPROM DATA IN: This pin is used as the serial input data signal from the EEPROM (65) (EED0)
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POWER SUPPLY PINS 36, 47, 48 AVCC +5V DC power supply for analog CKT. A decoupling capacitor should be connected between these pins and GND for analog CKT 43, 44, 51 AGND GND for analog CKT 1, 53, 72 +5V DC power supply for digital CKT. A decoupling capacitor should be connected betwneen these pins and GND for digital CKT 52,73,74, GND for digital CKT...
8-4 VT82580 VT82C585VP PIN DESCRIPTION Signal Name Pin No. Power Signal Description CLOCK CONTROL NCLK HOST CLOCK: This pin receives a buffered host clock. This clock is used by all of the VT82C585VP logic that is in the Host clock domain. This should be the same clock net that is delivered to the CPU.
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Signal Name Pin No. Power Signal Description HLOCK# HOST LOCK: All CPU cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic. CACHE# CACHEABLE: Asserted by the CPU during a read cycle to indicate the CPU can perform a burst line fill. Asserted by the CPU during a write cycle to indicate that the CPU will perform a burst write-back cycle.
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CALE/CE1# CACHE ADDRESS LATCH/CHIP ENABLE 1: This pin has two modes depending on the type of SRAM selected. 1. Async. SRAM: CALE is used to control the cache address latches. 2. Sync. SRAM: CE1 is used as chip -select 1 for the BSRAM.
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MSTB# dram MEMORY STROBE: Assertion causes data to be posted in the DRAM Write Buffer. HSTB# dram HOST STROBE: Assertion causes data to be posted in the CPU Read Buffer. CMD[4:0] 141-137 dram COMMAND: VT82C585VP uses these signals to control the buffers in VT82C587VP.
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GNT#[3:0] 154, GRANT: Permission is given to the master to use PCI. 156, 158, POWER AND GROUND VDD_CPU 10, 43, Power supply for the CPU bus. 61, 84 VDD_PCI 184, 201 Power supply for PCI bus. 147, 165 Power supply VDD_DRAM 97, 114, dram...
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PIN OUT IN NUMERICAL ORDER Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name HLOCK# CAS3# / DQM3# REQ2# M/IO# CAS5# / DQM5# GNTI# CAHCE# CAS1#/DQM1# REQ1# KEN# CAS4# / DQM4# GNT0# AHOLD CAS0# / DQM0# REQ0# SMIACT#...
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VT82C586 PIN DESCRIPTION Signal Name Pin No. Signal Description PCI Bus Interface PCLK PCI CLOCK: PCLK provides timing for all transactions on PCI Bus. FRAME# FRAME: Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator.
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LA23/DCS3B#, 63-67, 69-70 Multifunction Pins: LA22/DCS1B#, ISA Bus Cycles: LA21/DCS3A#, UNLATCHED ADDRESS: The LA[23:17] LA20/DCS1A#, address lines are bi-directional. These address LA[19:17]/ lines allow accesses to physical memory on ISA DA[2:0] bus up to 16mbytes. PCI IDE Cycles: CHIP SELECT: DCSIA# is for the ATA command register block and corresponds to CS1FX# on the primary IDE connector.
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IOCHCK# I/O CHANNEL CHECK: When this signal asserted, it indicates that a parity or an uncorrectable error has occurred for a device or memory on the ISAbus. IOCHRDY I/O CHANNEL READY: Devices on the ISA Bus negate IOCHRDY to indicate that additional time (wait states) is required to complete the cycle.
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SMI# SYSTEM MANAGEMENT INTERRUPT: SMI# is asserted by the VT82C586 to CPU in response to different Power-Management events. FERR# NUMERICAL COPROCESSOR ERROR: This signal is tied to the coprocessor error signal on the CPU. IGENN# IGNORE ERROR: This pin is connected to the ignore error pin on the CPU.
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XD Interface XD[7:0] 122-121,119- X-BUS DATA BUS: 116, 114-113 These pins are used as strap option during the power-up: XD0: 0/l - Disable/enable internal KBC XD1: 0/l - Disable/enable internal PS/2 Mouse. XD2: 0/l - Disable/enable internal RTC XD3: 0/l - PIA/SIO XD4~XD7: RP13~RP16 for internal KBC XDIR X-BUS DIRECTION: XIDR# is tied directly to the...
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MSCK / IRQ1 Multifunction Pin: PS/2 mouse enable: MOUSE CLOCK: CLOCK to PS/2 mouse interface. PS/2 mouse disable and internal KBC disable: INTERRUPT REQUEST 1: IRQ 1 input from external KBC. MSDT/ Multifunction Pin: IRQ12 PS/2 mouse enable: MOUSE DATA: DATA to PS/2 mouse interface. PS/2 mouse disable: INTERRUPT REQUEST 12: IRQ 12 input from external KBC...
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PIN OUT IN NUMERICAL ORDER Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name PIRQA# RTCX2 VDD-pci PCICLK DIORB# KEYLOCK PCIRST# DIOWB# TURBO RSTDRV HSOE# KBCK IOCHCK# DRQ5 KBDT DACK5 MSCK CBE0# DRQ2 DRQ0 MSDT IOCHRDY...
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VT82C587VP PIN DESCRIPTION Signal Name Pin No. Signal Description CPU Data Port HD[31:0] 24-17, 14- HOST DATA: These signals are connected to the 11, 9-2, 99- CPU data bus. The CPU data bus is interleaved 92, 89-86 between the two VT82C587VP for every byte, effectively creating an even and odd 587VP.
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PIN OUT IN NUMERICAL ORDER Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name PLINK6 MD26 HCLK HD12 PLINK5 MD10 HD13 PLINK4 VDD-dram CAS# HD14 PLINK3 MD18 RESET# HD15 PLINK2 DB32 HD16 PLINK1 MD27 HD17 PLINK0...
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ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Unit °C Ambient operating temperature °C Storage temperature Input voltage -0.5 Voltage Output voltage (V = 5v) -0.5 Voltage Output voltage (V = 3.1 - 3.6V) -0.5 + 0.5 Voltage Note: Stress above these listed cause permanent damage to device. Functional operation of this device should be restricted to the conditions described under operating conditions.
PENTIUM ® PROCESSOR with MMX Technology ARCHITECTURE OVERVIEW ® The embedded Pentium processor with MMX technology is binary compatible with the 8086/88, 80286, Intel386 , and Intel436 processor families, and with other Pentium processors. The embedded Pentium processor family includes the following products. * Pentium processor * Pentium processor with Voltage Reduction Technology * Pentium processor with MMX technology...
8-7 Power Supply (100W) The power supply used in the MP-2000 is a 100W open frame power supply. The specifications and features of this special power supply are listed in the following sections. Specifications • High efficiency 100W output •...
10-2. Customer Display 1. QT-7060D Item Code No. Parts Name Specification Price code R DISPLAY PWB (T) EAL-0449A (QT) 00-48500081 New U1 19300006 CPU M38022M4-314FP 00-00508500 New U4 19300005 S-RAM N345256SOA-55 00-00503820 19300004 EP ROM M27C4001-12F1 00-00502030 U3. 8 19300008 I C MC74HC00AFEL 00-00605500 19300009 I C...
Item Code No. Parts Name Specification Price code R Acrylic 19300030 FRONT-CASE 94090901(345) 00-24177131 Lens94090906 19300031 REAR-CASE 94090902(345) 00-24177141 INSULOCK TIE CV-075 00-40300500 PLASTIC BAG 300*400 00-30700170 GIFT BOX QT-7060D 00-30192080 c) New BOTTOM PAD QT7060/7062 00-22410603 c) New PROTECTION PAD QT7060 00-22410604 c) New...