Casio MP-2000 Service Manual page 68

CALE/CE1# 94
MA[11:0] 125-120,
118-115,
113, 112
RAS#[5:4] 103, 102
RAS#[3:0]/ 99-98,
CS#[3:0] 101-100
CAS#[7:0]/ 104, 110,
DQM#[7:0] 106, 108,
105, 111,
107, 109
WE# 95
SRAS#A-B 73,74
SCAS#A-B 92, 93
SWE#A-B 75, 76
MREQ0# 163
MREQ1# 166
MGNT# 162
DGNT# 126
DB32 88
PLINK[15:0] 151-148,
146-143,
134-127
cpu O
DRAM CONTROL
dram O
dram O
dram O
dram O
dram O
dram O
dram O
UNIFIED MEMORY INTERFACE
dram I
dram I
dram O
dram O
VT82C587VP INTERFACE
cpu B
dram B
— 67 —
CACHE ADDRESS LATCH/CHIP ENABLE 1: This pin
has two modes depending on the type of SRAM
selected.
1. Async. SRAM: CALE is used to control the cache
address latches.
2. Sync. SRAM: CE1 is used as chip -select 1 for the
BSRAM.
MEMORY ADDRESS: DRAM address lines.
ROW ADDRESS STROBE of each bank for
FPG/EDO/BEDO DRAM.
Multi-functional pins:
1. FPG/EDO/BEDO DRAM: ROW ADDRESS
STROBE of each bank.
2. Synchronous DRAM: chip select of each bank.
Multi-functional pins:
1. FPG/EDO/BEDO DRAM: COLUMN ADDRESS
STROBE of each byte line.
2. Synchronous DRAM: data mask of each byte lane.
DRAM write enable.
ROW ADDRESS COMMAND INDICATOR: for
Synchronous DRAM, two identical copies for better
driving.
COLUMN ADDRESS COMMAND INDICATOR: for
Synchronous DRAM, two identical copies for better
driving.
WRITE ENABLE COMMAND INDICATOR: for
Synchronous DRAM, two identical copies for better
driving.
MEMORY REQUEST 0: This pin is asserted by the
graphic controller to get access to local DRAM.
MEMORY REQUEST 1: This pin is asserted by the
graphic controller to get access to local DRAM (It is
reserved if 2 pin protocol selected)
MEMORY GRANT: VT82C585VP assert this pin to
relinquish DRAM bus to graphic controller.
DATA GRANT: Controls external buffer for UMA
interface.
DRAM WIDTH: to control VT82C587VP if 32-bit
DRAM is used.
PCI LINK: This is the data path between the CPU/main
memory and PCI. PCI main memory reads and CPU to PCI
writes are driven onto these pins by the VT82C587VP. CPU
reads from PCI and PCI writes to main memory are received
on this bus by the VT82C587VP. Each VT82C587VP
connected to one byte of this bus.