Table of Contents
Advertisement
Pine
Pin Name
127
MBD0
128
MBDI
129
MBD2
130
MBD3
131
MBD4
132
MBD5
133
MBD6
134
MBD7
135
MBD8
136
MBD9
137
MBD10
138
MBD11
140
MBD12
141
MBD13
143
MBD14
144
MBD14
106
MCD0
(VB2)
(EVID#)
107
MCD1
(VB3)
(VP0)
109
MCD2
(VB4)
(VP1)
110
MCD3
(VB5)
(VP2)
111
MCD4
(VB6)
(VP3)
112
MCD5
(VB7)
(VP4)
113
MCD6
(VG2)
(VP3)
114
MCD7
(VG3)
(VP6)
115
MCD8
(VG4)
(VP7)
116
MCD9
(VG5)
(VP8)
117
MCD10
(VG6)
(VP9)
118
MCD11
(VG7)
(VP10)
119
MCD12
(VR2)
(GRDY)
120
MCD13
(VR3)
(VP11)
121
MCD14
(VR4)
(VP12)
122
MCD15
(VR5)
(VP13)
Note:
S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for
one clock before released, and are not driven for at least one cycle after being released by the previous device. A
pull-up provided by the bus controller is used to maintain an inactive level between transactions.
Pin names in parenthesis (...) indicate alternate functions.
If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into "In circuit Test" (ICT)
mode. In ICT mode, all digital signal pins become inputs which are apart of a long path stating at ENAVDD (pin
62) and proceeding to lower pin numbers around the chip to pin 1 then to pin 208 and ending at VSYNC (pin 64).
If all pins in the path are high the VSYNC output will be high. If any pin is low, the VSYNC output will be low.
Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a
time and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XLTAI with
ICTENA# high or RESET# high will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins
except VSYNC. If TSENA# is low with RESET# low, a rising edge on XTLAI will 3-state all pins. An XTALI
rising edge without enabling conditions exits 3-state.
For the ZV Port interface, Y0-7 correspond to VP0-7, and UV0-7 correspond to VP8-15
Type
Active
Description
I/O
High
Memory data bus for DRAM B (upper 5I2KB)
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
Memory data bus for DRAM C (Frame Buffer)
I/O
High
I/O
High
When a frame buffer DRAM is not required, this bus may
I/O
High
be used to input up to 18 bits of RGB data from all external
I/O
High
PC-Video subsystem or 16 bits of RGB from an external
I/O
High
VAFC interface. Note that this configuration also provides
I/O
High
additional panel outputs so that a video input port may be
I/O
High
implemented along with a 24-bit true-color TFT panel (TFT
I/O
High
panels never need DRAM C). In VAFC interface mode, pin
I/O
High
106 is the VAFC "Enable Video" input. The external
I/O
High
VAFC interface drives this pin low to indicate data input on
I/O
High
the VPO-15 EVID# is ignored (essentially reserved) in the
I/O
High
65550 (VAFC data is always expected as inputs). In VAFC
I/O
High
mode, pin 119 is "Graphics System Ready" out and is
I/O
High
always driven high.
I/O
High
— 48 —
Advertisement
Chapters
Table of Contents
