Casio MP-2000 Service Manual page 67

Signal Name Pin No.
HLOCK# 53
CACHE# 55
AHOLD 57
NA# 63
BOFF# 64
SMIACT# 58
COE# 72
CWE#[7;0] / 76-73,
SWE#A-B, 93-90
SRAS#A-B,
SCAS#A-B,
BWE#,
GWE#
TWE# 89
A3SEL/ 71
CADS#
A4SEL/ 70
CADV#
TA[9] / DB32 88, 87,
TA[8:0] 80, 81,
82, 85,
86, 79-77
Power I/O
cpu I
cpu I
cpu O
cpu O
cpu O
cpu I
CACHE CONTROL
cpu O
cpu O
cpu O
cpu O
cpu O
cpu B
— 66 —
Signal Description
HOST LOCK: All CPU cycles sampled with the
assertion of HLOCK# and ADS#, until the negation of
HLOCK# must be atomic.
CACHEABLE: Asserted by the CPU during a read cycle
to indicate the CPU can perform a burst line fill. Asserted
by the CPU during a write cycle to indicate that the CPU
will perform a burst write-back cycle.
ADDRESS HOLD: The VT82C586 asserts AHOLD
when a PCI master is accessing main memory. AHOLD
is held for the duration of the PCI burst transfer.
NEXT ADDRESS:
BACK OFF: Asserted by the VT82C585VP when
required to terminate a CPU cycle that was in progress.
SYSTEM MANAGEMENT INTERRUPT ACTIVE:
This is asserted by the CPU when it is in system
management mode as a result of SMI.
CACHE SRAM OUTPUT ENABLE:
Multi-function pins:
Global write option off (bit 2 of RX54h is 0): Cache
SRAM write enable or each byte.
Global write option on (bit 2 of RX 54h is 1):
Synchronous DRAM command indicators and
BWE#/GWE# for global write SRAM control.
TAG WRITE ENABLE: When asserted, new state and
tag addresses are written into the external tag.
CACHE ADDRESS 3/CACHE ADDRESS STROBE:
This pin has two modes depending on the type of SRA
selected.
Async. SRAM: A3SEL is used to sequence through the
Qwords in a cache line during a burst operation.
Sync. SRAM: Its assertion causes the burst SRAM load
the BSRAM address register from BSRAM address pin.
CACHE ADDRESS 4/CACHE ADVANCE:
This pin has two modes depending on the type of SRA
selected.
Async. SRAM: A4SEL is used to sequence through the
Qwords in a cache line during a burst operation.
Sync. SRAM: its assertion causes the burst SRAM to
advance to advance to the next Qword in the cache line.
TAG ADDRESS: These are inputs during CPU accesses
and outputs during L2 cache line fills and L2 line
invalidates during inquire cycles.
TA9 is a multi-function pin. It will act as DB32 to
VT82C587VP when 32bit DRAM mode is enable.